Wide technology range
Mirafra delivers Analog and Mixed signal design and layout across a wide spectrum of process nodes—from legacy 500nm CMOS to cutting-edge 18A technologies. We support bulk CMOS, BiCMOS, BCD, FDSOI, FinFET, GAA platforms, adapting our design methodology to each node's specific challenges. Our process-aware approach ensures reliability and performance optimization across various foundries like TSMC, Samsung, Intel, TI GF, UMC, Micron, Maxim, Infineon etc., handling full-chip, module and IP level solutions.
Power management
Our power management design capabilities include LDOs, Bandgap references, DC-DC converters, battery monitors, and voltage regulators for low-power applications. We optimize for efficiency, ripple suppression, and load regulation while meeting stringent safety and thermal requirements. These circuits are widely used in mobile, IoT, and automotive domains.
Clock systems and Data converters
Expertise in PLL, DLL, clock buffers, and oscillator design for precise timing and low jitter. Our high-speed ADC, DAC , TDC converters are optimized for resolution, sampling rate, and dynamic range.
RF layout
Our skilled Mixed signal layout engineers are experienced in handling complex high speed RF layout constraints, including symmetry, shielding and parasitic optimization. Working on RF frontend Rx/Tx, Power Amplifier, Signal Detectors, Local Oscillators, LNA, PGA, Mixers, PLL, Synth, VCO, Slicer, DAC, ADC, DLL, WLAN RX & Tx, UWB Rx Tx, Bluetooth blocks with a keen focus on signal integrity and performance matching.
Analog and Mixed-Signal IC Design
Our IC design methodology combines top-down architecture development with bottom-up block-level implementation, ensuring robust performance across full-chip conditions. We integrate multiple analog blocks into SoCs with well-defined interfaces and reliable floor planning, using industry EDA tools from Cadence, Mentor Graphics and Synopsys.
IO buffer solution
Design of general-purpose IO buffers, high speed LVDS and high speed IOs. These buffers meet JEDEC and foundry-specific compliance standards. Team comprises of engineers skilled in circuit design, layout and characterisation of IO buffers.
Analog Mixed-Signal Layout Design
Our highly skilled analog layout engineers work on the entire full chip layout development from area estimation to final release. This involves chip level floor plan with critical discussion with chip lead as per the signal flow, power plan taking into account the current and IR drop requirements of modules. Floor plan reviews is followed by module level routing and full chip hook up. Final hand off is done after multiple levels of reviews of signal and power plan. Our layout team ensures first-time-right silicon by following foundry DRC/LVS rules, minimizing parasitic mismatches, and managing layout-dependent effects (LDE). Familiar with all the industry level tools Cadence/Synopsys/Mentor Graphics
