Unleashing the power of semiconductor solutions

Formal Verification

Location: Hyderabad

Job Description:

Jasper Gold experience, CC checks, Property checks and IOMUX verification

Experience (years) : 4-6 yrs

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Emulation Engineer

Location: Bangalore

Job Description:

• Experience in SIMXL / Emulation platform bring-up & debug (including Simulation acceleration setup)
• Knowledge of C/C++ coding
• Familiarity of SoC testbench & boot-up flows The current role requires emulation test bring-up at the SoC level, including boot flow knowledge, Zebu build creation, and debug capabilities (waveforms, C loggers).

Experience (years) : 4-8 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

FPGA

Location: Hyderabad

Job Description:

• Responsibilities include packing RTL files into IP using AMD packaging methodology
• Excellent TCL and PERL/Python concepts and experience in Verilog / System Verilog design and verification.
• Working knowledge of UNIX environment desired.

Job Requirement:

• Expertise with FPGA architecture and Xilinx-AMD, Vivado
• Debug skills using tools like VCS, xcelium and Questa.

Experience (years) : 3-6 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

FPGA

Location: Hyderabad

Job Description:

• Exp on Video domain IPs / Digital IPs.
• Exp of one or more of protocols at the IP level: MIPI CSI / MIPI DSI / DisplayPort /HDMI / SDI.

Job Requirement:

• Hands on experience with architecting / micro-architecture.
• Verilog/ System Verilog RTL coding for FPGA designs.
• Lint, CDC, synthesis flow and static timing flows, formal checking, etc. experience.

Experience (years) : 7-12 yrs

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Validation Engineer

Location: Hyderabad

Job Description:

• Good knowledge of Vivado, HDL
• Familiar with Vitis.
• Having C knowledge and experience in building BareMetal application is big +ve

Job Requirement:

• Should be able to build IPI based system
• Should be able to design small debug modules, develop validation systems

Experience (years) : 4-6 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Design Verification(Ethernet/Wifi/BT)

Location: Pune

Job Description:

Ethernet/Wifi/BT verification. Strong in SV,UVM.

Experience (years) : 4+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Design Verification(High Speed Protocol)

Location: Bangalore

Job Description:

• PCIE/DDR/LPDDR/CXL/UCIE/Ethernet are good to have protocols, Arm experience, GLS
• Initial work at subsystem level followed by SoC level execution
• Expertise on Ethernet protocol/Expertise on packet processing in networking data path.
• High speed ethernet experience 400G+ is preferred.

Experience (years) : 4+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Design Verification (Cache)

Location: Bangalore

Job Description:

DV (Cache Coherence, Amba, Axi, Chi, DDR in future) – open for good numbers of positions in IP DV domain

Experience (years) : 4+ years

Education Qualification:

BE/ME

Design Verification(SOC)

Location: Bangalore

Job Description:

•Verification engineer with a knowledge of SoC integration verification, SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx/AI accelarator integration verification in SoC RTL.
•Your key responsibilities will include writing test plans, defining test methodologies, developing C based software tests, SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues.
•Working with project management and leads on planning tasks, schedules, and reporting progress
•Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development

Job Requirement:

Proven understanding of digital hardware verification language Verilog/System Verilog HDL.

Experience (years) : 5+ years

Education Qualification:

BE/ME

Design Verification(GLS)

Location: Bangalore

Job Description:

Verification Engineer with over 4 years of experience in Gate-Level Simulation (GLS).
Skilled in UVM, SystemVerilog, and industry-standard verification methodologies.
Strong in debugging, timing analysis, and simulation to ensure design accuracy and performance.
Key Skills HDL/HDVL: Verilog, System Verilog
Tools: Synopsys VCS, Verdi, DVE GLS
Expertise: Zero Delay (ZD), SDF, Power-Aware GLS (PAGLS)
Others: Low-Power Verification, RTL Debug, UVM Environments

Experience (years) : 4+ years

Education Qualification:

BE/ME

Design Verification Engineers

Location: Noida

Job Description:

• SOC Verification engineers with 3+ years of experience
• Knowledge of ARM architecture, CPU fundamentals & Cache coherency
• Experience with C/C++, assembly, and scripting languages.
• Familiarity with low-power design and verification
• Develop CDV UVM verification environments at system level
• Verify CPU connectivity to IP blocks
• Develop SoC test plans and test cases and track metrics including code and functional covera

Job Requirement:

• Bachelor’s or Master’s in EE/CS or related field
• 3+ years of SoC in ASIC/FPGA verification experience
• Proficiency in SV and UVM
• Experience with simulation, emulation, and formal verification
• Strong debugging and problem-solving skills

Experience (years) : 3+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Analog Layout

Location: Bangalore / Hyderabad

Job Description:

• TSMC 16/12nm,7nm,5nm,3nm and below (other foundries are also fine like Intel, Samsung, GF). Preferably TSMC 5nm/3nm experience.
• Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.
• Verification flows – LVS/DRC/DFM/Antenna check/EMIR experience.
• Responsible for on-time delivery of block-level layouts of acceptable quality.
• Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must.
• BE or MTech in Electronics/VLSI Engineering
• Good communications skills as we work with cross-functional teams.
• Share the profiles who have good hands-on experience in recent times on lowers nodes.
• TM should work independently.
• 4 to 8 years of experience – flexible
• If a candidate has HBM experience, it is an added advantage. Analog blocks like Regulators/Charge pumps/Power Management etc..

Job Requirement:

TSMC 2nm or 3 nm

Experience (years) : 4-8 years

Education Qualification:

BTech

Analog Circuit Design

Location: Bangalore / Hyderabad

Job Description:

• High speed DDR IO Circuit Design JD: (Experience level 2 year to 6year)
• Strong fundamental in Circuit design. Knowledge of finfet.
• Work experience in high speed transreceiver, Prior work experience in high speed TX, RX.
• Knowledge of ESD, Latchup.
• Experience in layout related issue. Strong debug capability.
• Experience in .lib/Verilog view generation and validation.
• Scripting knowledge is Plus.

Experience (years) : 5-9 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

IO Layout

Location: Bangalore

Job Description:

• Very Good Knowledge on GPIO layouts and performing Layout verifications.
• Good Exposure to Technologies of GF 55nm , UMC 55nm , TSMC 28nm, TSMC 12nm etc.
• Should have Solid experience in Layout design and Verifications of all the blocks of a GPIO library like Driver, predriver, receiver, ESD clamps.
• Should be in position to technically drive the Layout Implementation starting with floorplanning, placement , IO ring Implementation , IO Bus design .
• Very good hands on knowledge on the Cadence Virtuoso layout verification suite relevant to the above mentioned technologies.
• Very good understanding of ESD & LU concepts and corresponding Layout Implementation strategies and challenges.
• Working (hands on) knowledge of Linux OS and Unix Shell & PERL scripting will be a plus.
• Good team player in a multi-site work environment
• Working knowledge with load sharing systems like LSF will be a plus. Very Good Knowledge on GPIO layouts and performing Layout verifications.
• Good Exposure to Technologies of GF 55nm , UMC 55nm , TSMC 28nm, TSMC 12nm etc.
• Should have Solid experience in Layout design and Verifications of all the blocks of a GPIO library like Driver, predriver, receiver, ESD clamps.
• Should be in position to technically drive the Layout Implementation starting with floorplanning, placement , IO ring Implementation , IO Bus design .
• Very good hands on knowledge on the Cadence Virtuoso layout verification suite relevant to the above mentioned technologies.
• Very good understanding of ESD & LU concepts and corresponding Layout Implementation strategies and challenges.
• Working (hands on) knowledge of Linux OS and Unix Shell & PERL scripting will be a plus.
• Good team player in a multi-site work environment
• Working knowledge with load sharing systems like LSF will be a plus.

Experience (years) : 4-9 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Memory Layout

Location: Bangalore

Job Description:

• 3-8 years of experience in Memory/Custom Layout design.
• Memory Leafcell layout library design from scratch including top level integration.
• Good knowledge on different types of memory architectures.
• Good knowledge in optimized layout design for better performance.
• Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations.

Job Requirement:

• TSMC 2 & 3 NM

Experience (years) : 5-7 years

Emulation Engineer

Location: Bangalore

Job Description:

• Create emulation models from RTL / Netlist.
• Expertise in mapping designs to Zebu/Palladium/Haps emulation, improving model performance.
• Knowledge of the Palladium flow and experience in migrating design on Palladium.
• Good knowledge of runtime and debug skills.
• Identifying signals and taking wave dumps on palladium platforms and analyse the failures.

Good to have Skills:
• Exposure to ARM/ARC cores and its architecture
• Exposure to AMBA bus architectures like AXI/AHB/APB
• Exposure to bug tracking tools like Jira and version control tools like Github, Bitbucket, GIT
• Exposure to Flash(NAND) and HDD(Hard disk) like storage technologies.
• Experience with Palladium like emulation platforms(Veloce or Zebu or Haps)
• Understanding of JTAG based debuggers

Job Requirement:

• 6+ years of experience on emulation platform builds and design integration.

Experience (years) : 6+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

RTL Design

Location: Bangalore

Job Description:

• Must have expertise on processor based SoC design which includes (but not limited to), ARM processor, DMAs, power/clock/reset controllers, interfaces like
  USB/SDIO/PCIe/SPI/UART
• Must have good understanding of high-speed interfaces like USB, SDIO, PCIe and proven track record in such developments.
• Expertise in System Verilog/VHDL languages.
• Expertise with scripting CDC/ LINT checks UPF and CLP for multi power, multi voltage domains. Verilog, UPF / CLP, CDC, LINT

Experience (years) : 7+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

RTL Microarchitecture

Location: Bangalore

Job Description:

• Strong understanding of the design convergence cycle, including architecture, micro-architecture, Verification, Synthesis and timing closure.
• Expertise in managing IP dependencies, as well as planning front-end design tasks.
• Design and development of high-speed serial IO protocols
• Implementation of clock rate compensation FIFO, gearbox design for data width, bypass on controller, power gating, low power modes
• Experience in CPU, bus fabrics, or coherence/noncoherent NOC domains is highly desirable.
• Excellent communication and interpersonal skills.
• Ability to collaborate in a fast-paced, product-oriented, and distributed team environment.

Job Requirement:

• Micro Architecture Development: Ability to develop micro-architecture based on specifications.
• Bus Protocols & Peripherals: Strong knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc.
• Memory Controllers & Microprocessors: Experience with memory controller designs and microprocessors is an advantage.
• Chip IO Design: Knowledge of chip IO design and packaging is beneficial.
• Test Plans & Verification: Proficient in reviewing high-level test plans and coverage metrics.
• Synthesis & Formal Verification: Expertise in Design Compiler Synthesis and formal verification using LEC.
• Timing Closure: Comprehensive understanding of timing closure is mandatory.
• Post-Silicon Debug: Experience in post-silicon bring-up and debugging

Experience (years) : 10+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

PD CAD

Job Description:

• VLSI CAD Engineer with extensive Python Experience.
• CAD development role using python to develop workflows, approval, analytics dashboards, notification system, IP version differences.
• 5+ years experience in an CAD role
• Proficiency in Python, Workflows and SQL
• Knowledge of AI Agentic Architecture and RAG techniques
• Preferred experience in creating dashboards and flows that interface with VLSI CAD tools or data used/generated in the chip design process
• LookerStudio or Tableau experience
• Driven team player with good communication skills
• Proactive in shaping spec and architectural direction, rather than just executing tasks.

Experience (years) : 5+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

PD

Location: Bangalore

Job Description:

• Should have worked on the entire PD Flow from netlist to GDS (Floorplanning, Power Planning, Placement & Optimization, CTS, Routing, ECO steps, Timing/SI)
• Should have very good idea about OCV/MM/MC and multi power designs (Level shifters, Isolation cells .
• Should have worked extensively on XTalk/SI/EM
• Should be familiar with DSM topics like OPC/CMP etc for 65nm and lower technologies.
• Should be very strong on CTS constraints and skew fixing.
• Tool specific knowledge: : Cadence: Innovus, Calibre, Tempus
• Good understanding of library preparation in any environment (Synopsys, Magma or Cadence)
• Knowledge of DRC/LVS, IR Drop, Formal Verification and Synthesis an added advantage.
• Job would require complete ownership from netlist to GDS for blocks. Should have done similar job well in the past
• Should have worked on 65nm and lower technologies.

Experience (years) : 3+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

STA

Location: Bangalore

Job Description:

• At least 4-5years of actual industry experience.
• Good Experience with writing constraints.
• Analyzing timing reports.
• Basic scripting knowledge.
• Basic understanding of RTL.
• Experience with PT(Primetime) and can write DC/PT timing constraints.
• Collaborate with physical design and synthesis teams to resolve timing violations.
• Analyze timing paths and optimize for setup, hold, and clock skew issues.
• Work on multi-voltage domains and low-power design techniques (e.g., UPF).
• Support timing signoff and tape-out activities.

Job Requirement:

• Strong understanding of STA fundamentals and timing closure methodologies.
• Proficiency in tools like PrimeTime, Tempus, Tweaker, Timevision, Fishtail.
• Experience with scripting languages (TCL, Perl, Python) for automation.
• Familiarity with advanced nodes (e.g., 7nm, 5nm, FinFET).
• Good grasp of physical design flow and constraints management.
• Ability to debug timing issues and propose effective solutions.

Experience (years) : 4+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

DFT

Location: Bangalore

Job Description:

• Hands on experience in Tessent DFT RTL insertion, DRC checks and debug is a must.
• Hands on experience on Scan Insertion, ATPG, GLS debug, MBIST pattern generation and validation.
• Working knowledge of timing enabled GLS and related debug.
• A basic understanding of DFT IPs like OCC, EDT, SSN, MBIST controllers, IJTAG, IEEE 1600 standard, and Boundary scan.
• Should be able to handle tasks independently.
• The candidate needs to have good debug skills and should be able to communicate related issues to the larger team.
• Working knowledge of TCL is an add-on.

Experience (years) : 4+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

PD

Location: Hyderabad

Job Description:

• Responsible for supporting Place and Route flows for various designs at 6nm, 4nm and 3nm technology nodes
• Tool versions qualification & deployment of new features into the flow
• Updating existing flows for new capabilities as required
• Hands on experience in Synopsys Fusion Compiler or ICC2
• Good control over scripting languages like PERL, TCL and strong debug capabilities
• Hands on experience in synthesis, place and route flows and STA tools
• Hands on experience with physical verification tools PnR flow qualification, Running multiple PnR blocks to benchmark QOR, Running STA, EMIR, PDV signoff flows

Experience (years) : 6-10 years

Education Qualification:

BE/ME

AMS Verification

Location: Bangalore

Job Description:

• Experience on verifying PMICs or Mixed-Signal products.
• Lead verification of analog and mixed-signal blocks, including but not limited to bandgaps, LDOs, Buck multi-phase switching regulators, comparators, and FuSa monitoring circuits.
• Own the verification plan for assigned blocks or features, ensuring thorough coverage and high-quality tests.
• Develop and/or update models of analog blocks using SV-RNM.
• Understand and verify digital functionalities such as CRC, Clock Monitoring, Register maps, and OTPs, Communication Interfaces.
• Understanding of SystemVerilog including assertions and covergroups.
• Advanced debug skills including RTL and Schematic debug from the top level.
• Create and manage VSIF files for regression.
• Ability to perform coverage analysis using IMC or vManager.
• Makefile scripting is a plus.
• Ability to work independently under broad direction.

Job Requirement:

• AMS Verification

Experience (years) : 3+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Verification

Location: Hyderabad

Job Description:

• Must have good knowledge on the verification flows
• Excellent hands-on debug skills and problem solving attitude.
• Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC
• Experience of working on Functional Verification, SoC Verification, Emulation
• Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language OVM/UVM Methodology knowledge and experience.
• Must have good communication skills and the ability to work in a team environment.
• Preferably having experience in architecture such as x86 or ARM domain based SOCs
• Having SOC/IP performance verification background is added plus

Job Requirement:

•Processor / PCI / DDR / Memory/C/C++

Experience (years) : 5-15 years

Education Qualification:

BE / ME

Design Verification Engineers

Location: Bangalore

Job Description:

• Working experience in IP/SoC/Subsystem/verification
• Strong understanding of computer architecture and ASIC design flow
• Experience in UVM
• Experience in Verilog and System Verilog languages
• Experience with PCIe/DDR/USB/Ethernet/CXL/HDMI/MIPI/DSI/CS/GLS/CPU Verification
• Experience with hands on IP integrations into SOC is a plus
• Excellent debug skills.
• Experience in assembly language or C is a plus
• Familiar with scripting (Python/Perl/Shell)
• Experience with assertion-based design strategies, code coverage, functional coverage and test plan development.
• Should have excellent communication skills (both written and oral)
• Strong problem-solving skills

Job Requirement:

• Bachelor’s or Master’s in EE/CS or related field
• 5+ years of SoC in ASIC/FPGA verification experience
• Proficiency in SV and UVM
• Strong debugging and problem-solving skills

Experience (years) : 5+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

ATE

Location: Bangalore

Job Description:

• Design, develop, and implement ATE solutions to automate testing for new and existing products
• Create test plans, procedures, and test cases based on product specifications and requirements.
• Write test software scripts using languages such as Python, C++, or similar to interface with ATE hardware.
• Troubleshoot and debug issues in test equipment and software to identify root causes and implement corrective actions.
• Perform analysis of test data and report findings to engineering teams for further improvements.
• Collaborate closely with hardware, firmware, and design teams to ensure test coverage and validation of key product features.
• Maintain and upgrade ATE systems to meet evolving testing needs

Job Requirement:

• Experience in Verigy93K- SMT8

Experience (years) : 3-10 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

PMIC Char

Location: Bangalore

Job Description:

• Provide post-silicon validation support, drive interactions with Design, Test, Product
• Quality Engineering to resolve product issues.
• Perform silicon evaluation at chip/board level and document errata to support necessary device modifications. Proficient in design-of-experiment to help isolate issues and get to root-cause on analog and mixed-signal products.
• Proficient with large-scale mixed-signal 5.PMIC(power management IC) such as bucks, boost, LDOs, ADC, GPIO, I2C, SPMI
• Proficient in automation using Python for automated measurements.
• Ability to run temperature characterization using thermal-stream and/or oven

Experience (years) : 4-12 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Functional Validation with Python scripting

Location: Bangalore

Job Description:

• Good at SoC topics
• Reset concepts
• Clock concepts
• Multiple COM protocols
• Python scripting
• Strong in C and C++, linkers, memory organization, resource partition and handling
• Added advantage of Perspec(Cadence Flow)
• Good at Silicon Debug

Experience (years) : 3-8 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Functional Validation

Location: Bangalore

Job Description:

• Strong Experience on programming in C
• Experience on system debug, embedded operating systems, or bare metal programming
• ARM CPU architecture knowledge
• Pre-Silicon(Emulation) , Post Silicon experience

Job Requirement:

• Experience on JTAG debuggers (e.g., Lauterbach)
• Familiarity with CPU uArch and coherent fabric
• Post silicon debug expertise.
• Familiarity with ARMv8/ARMv9

Experience (years) : 4-10 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Design Verification Engineers

Location: Noida

Job Description:

• SOC Verification engineers with 3+ years of experience
• Knowledge of ARM architecture, CPU fundamentals & Cache coherency
• Experience with C/C++, assembly, and scripting languages.
• Familiarity with low-power design and verification
• Develop CDV UVM verification environments at system level
• Verify CPU connectivity to IP blocks
• Develop SoC test plans and test cases and track metrics including code and functional covera

Job Requirement:

• Bachelor’s or Master’s in EE/CS or related field
• 3+ years of SoC in ASIC/FPGA verification experience
• Proficiency in SV and UVM
• Experience with simulation, emulation, and formal verification
• Strong debugging and problem-solving skills

Experience (years) : 3+ Year

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

DFT Engineers

Location: Noida

Job Description:

• Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IJTAG. and MBIST/LBIST.
• Experience in Tessent based ATPG flow, GLS and Post-silicon-debug.
• Hands-on in Perl/Tcl/Python scripting.
• Excellent analytical, and problem-solving skills.
• Perform Core and SOC level ATPG to meet Automotive grade quality.
• Hierarchical ATPG retargeting and Pattern release for application on ATE.
• Perform SOC and Core level Timing/Non-timing GLS.
• Silicon bring-up, diagnosis and support for physical failure analysis.
• Enable Emulation of Gate level SCAN patterns.

Experience (years) : 5+ Year

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Physical Design Engineers

Location: Noida

Job Description:

We are looking for bright Physical Design Engineer with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering High performance design, flows for high performance SoCs in sub-10nm process for mobile space.

Job Requirement:

• 2-5 years hands-on experience of different PnR steps including Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure.
• Well versed with high frequency design & advanced tech node implementation
• In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience.
• In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation.
• Well versed with tackling high placement density/congestion bottlenecks.
• In depth knowledge of PnR tool knobs/recipes for PPA optimization.
• Experience in automation using Perl/Python and tcl.
• Good communication skills and ability & desire to work in a cross-site cross-functional team environment.

Experience (years) : 3+ Year

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

STA Engineers

Location: Noida

Job Description:

• Experience with STA using Primetime and PTPX required
• Proficient in constraint generation.
• Experience of multiple power domain implementation with complex UPF/CPF definition required
• Formal verification experience (Formality/Conformal)
• Perl/Tcl scripting is required
• Strong problem solving and ASIC development/debugging skills.
• Experience with CPU micro-architecture and their critical path.
• Low power implementation techniques experience.
• High speed CPU implementation.
• Place and route tool experience.
• Constraint management tool and Verilog coding experience

Experience (years) : 3+ Year

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

RTL Design Engineers

Location: Bangalore, Hyderabad, Noida

Skills/Experience:

• Strong design fundamentals with hands-on experience in front-end design flows
• Hands-on experience in design of micro-architecture blocks, RTL coding, block-level verification.
• Hands-on experience in Linting, CDC – analysis of reports, identify ways to fix the violations
• Hands-on experience in SoC/IP integration
• Excellent understanding of SoC components like processors, memories, peripherals, IOs
• Good understanding of at-least one of the protocols like UFS/PCIe/SAS/SATA/USB
• Experience of working with ARM or ARC (Synopsys) processors/sub-systems
• Experience of UPF flow, updating constraints
• Ability to work independently, ramp-up quickly and work with verification/validation teams for front-end flows
• Good experience in PERL/TCL scripting
• Good verbal and written communication skills are required.

Experience (years) : 3 - 12 Years

Education Qualification:

BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field

Analog Mixed Signal Layout

Location: Bangalore, Hyderabad, Noida

Skills/Experience:

• Independent layout development of High Speed blocks like SerDes, Rx, Tx, , PLL, ADC, LDO, Bandgap etc
• Strong debug skills and good communication

Experience (years) : 3 - 7 Years

Education Qualification:

BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

DFT Engineers

Location: Bangalore, Hyderabad, Noida

Skills/Experience:

• Proficient in Scan, specializing in ATPG and Pattern verification at Block and Full chip level.
• Skilled in Scan insertion, ATPG, DRC analysis, Low Coverage Analysis, JTAG and IJTAG.
• Experienced in scripting for flow automation, using Siemens tools (Tessent), Synopsys tools (DFTMAX, Tetra MAX, VCS, DFT Compiler), Verdi.
• Familiar with tools: NC-SIM/Irun, Sim-Vision, XCELIUM.

Experience (years) : 3+ Year

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

High Speed DDRIO

Location: Bangalore, Hyderabad, Noida

Skills/Experience:

• Work experience in high speed transreceiver, Prior work experience in high speed TX, RX. Knowledge of ESD, Latchup.
• Experience in layout related issues and strong debug capability.

Experience (years) : 4+ Year

Education Qualification:

BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

AL/ML Engineer

Location: Hyderabad

Job Requirement:

• Proficiency in Python and at least one additional language
• Experience with C/C++, Java, C#, Bash, PowerShell
• Hands-on experience implementing functionality beyond standard libraries
• Experience in building/training models using PyTorch, TensorFlow, TorchRL
• Knowledge of LLMs, multimodal models, computer vision
• Experience with SQL, Windows/Linux (Debian, RHEL) troubleshooting
• Understanding of QA and CI workflows
• Strong knowledge of Windows OS internals, device manager
• Experience with debugging and issue isolation in Windows kernel and driver modules
• Good understanding of PC hardware, SoC, chipsets, graphics cards, BIOS, VBIOS
• Strong analytical, problem-solving, and OOP skills
• Good verbal & written communication skills
• Positive attitude and ability to deliver on next-gen technology

Experience (years) : 2 - 4 Year

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Devops Engineer

Location: Bangalore

Job Description:

• Manage IP and release processes • Migrate repositories from ClearCase to Git or Perforce

• Set up CI/CD pipelines on top of the chosen SCM • Run and maintain automated tests and sanity checks Required Skills

• Strong experience with Git / GitLab / Perforce (preference in that order)

• Hands-on with Jenkins (pipeline creation, admin, troubleshooting)

• GitLab Runner or similar CI runners

• Unix/Linux environment familiarity

• Scripting in Python is Must

Job Requirement:

• Manage IP and release processes

• Migrate repositories from ClearCase to Git or Perforce

• Set up CI/CD pipelines on top of the chosen SCM

• Run and maintain automated tests and sanity checks Required Skills

• Strong experience with Git / GitLab / Perforce (preference in that order)

• Hands-on with Jenkins (pipeline creation, admin, troubleshooting)

• GitLab Runner or similar CI runners

• Unix/Linux environment familiarity

• Scripting in Python is Must

Experience (years) : 3+ Year

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Multimedia- Video/V4L2

Location: Hyderabad

Job Description:

Experience in Android and Linux Multimedia frameworks and Linux Kernel development with a focus on V4L2. Experience in Java/perl/python programming.
– Knowledge of software design patterns and multi-threaded programming.
– Knowledge of computer architecture, operating systems, data structures, and basic algorithms, particularly with respect to Linux/Android platforms.
– Software debugging skills in embedded real time operating systems, preferably on Linux platforms
Additional experience in one or more of the following areas:
– Video usage models including playback, streaming, camcorder, WiFi display, and content protection
– Video compression standards (e.g. H264/H.265/AV1)
– Streaming protocols and implementation (e.g HLS/HTTP/DASH)
– Linux device driver development and debugging (e.g. V4L2)
– Expertise in working with tools and techniques used on Linux (Windbg, JTAG, etc.)
– ARM or other embedded SoC development and debugging

Job Requirement:

• Bachelors\Master’s degree in Engineering, Information Systems, Computer Science, or related field 3-5 years of experience with Programming Language such as C, C++, Java, Python.

Experience (years) : 3+ Year

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Multimedia Audio DSP

Location: Hyderabad

Job Description:

Experience of 3+years or more on any DSP/Embedded processor with proficiency in C/C++ programming, computer architecture, operating systems and some of the below areas :

1.Knowledge of multi-threaded programming.
2.Strong software debugging skills in real time operating systems, preferably on DSP platforms.
3.Audio use cases (e.g. playback, recording and streaming, etc.).
4.Voice use cases (e.g. CS and PS calls).
5.Optimization for MIPS, Memory,Audio/speech pre/post processing (e.g. Echo cancellation, Noise suppression, Audio Effects) Audio/speech compression standards (e.g. MP3, AAC, FLAC, AMR, EVS, etc.).
Android Audio HAL and framework knowledge

Job Requirement:

• Bachelor’s degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Software Engineering or related work experience.

• 3+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc.

Experience (years) : 3+ Year

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Analog Circuit Simulations

Location: Bangalore, Hyderabad, Noida

Skills/Experience:

• Proficient in analog circuit simulations and characterisation for blocks like SerDes Rx Tx
• Strong fundamentals and knowledge of high-speed custom digital

Experience (years) : 2+ Year

Education Qualification:

BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

Analog Circuit Design

Location: Bangalore, Hyderabad, Noida

Skills/Experience:

• Experience with high speed circuits like serializer, deserializer, Rx, Tx,PLL, ADC etc
• Strong VLSI Fundamentals, Circuits design & Digital Systems deep submicron CMOS design based on FinFETs technology.
• Solid fundamentals in circuit analysis and Clock/Memory Circuit design.

Experience (years) : 2+ Year

Education Qualification:

BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

IO Layout

Location: Bangalore, Hyderabad, Noida

Skills/Experience:

• Strong experience in Layout design and Verifications of GPIO library
• Expertise in floorplanning, placement , IO ring Implementation and IO Bus design

Experience (years) : 3+ Year

Education Qualification:

BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

PMIC Characterization

Location: Bangalore, Hyderabad, Noida

Skills/Experience:

• Good knowledge on PMIC (power management IC) hardware validation engineers.
• NPU Architecture: Broadcom – preferable – Qumran/Jericho family
• Labview expertise is a good to have expertise.
• Good understanding of Switching and Linear Voltage Regulators

Experience (years) : 2 - 7 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

FPGA Design Engineer

Location: Bangalore, Hyderabad, Noida

Skills/Experience:

• Good Experience with Xilinx FPGA.
• Should be well aware of RTL logic.
• Well versed with Vivado tool and associated IP’
• Well versed with LUT considerations in FPGA design
• Well versed with FPGA simulation and testing methods
• Well versed with FPGA debug using Xilinx JTAG debugger

Experience (years) : 3 - 12 Years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Emulation Engineer

Location: Bangalore, Hyderabad, Noida

Skills/Experience:

• Create emulation models from RTL / Netlist.
• Expertise in mapping designs to Zebu/Palladium/Haps emulation, improving model performance.
• Knowledge of the Palladium flow and experience in migrating design on Palladium.
• Good knowledge of runtime and debug skills.
• Identifying signals and taking wave dumps on palladium platforms and analyse the failures.
• Exposure to ARM/ARC cores and its architecture
• Exposure to AMBA bus architectures like AXI/AHB/APB
• Exposure to bug tracking tools like Jira and version control tools like Github, Bitbucket, GIT
• Exposure to Flash(NAND) and HDD(Hard disk) like storage technologies.
• Experience with Palladium like emulation platforms(Veloce or Zebu or Haps)
• Understanding of JTAG based debuggers

Experience (years) : 3 - 12 Years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Physical Verification Engineer

Location: Bangalore, Hyderabad, Noida

Skills/Experience:

• Hands on debugging skills in different physical verification checks like LVS, DRC, ERC, PERC, Antenna, ESD and DFM using Calibre, ICV and Pegasus PV tools
• Knowledge of basic device physics and PV fixing using various PnR tools like Innovus/ICC2 is required.
• Working experience in cutting edge technologies such as 3/4/5nm and 7nm process nodes is desired

Experience (years) : 4+ Year

Education Qualification:

B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent

STA Engineers

Location: Bangalore, Hyderabad, Noida

Skills/Experience:

• Proficient in STA timing fixes, ECO and Synthesis of complex SOCs at Sub system level, Block level and Chip level.
• Tools: Design compiler, Prime time, Tempus

Experience (years) : 3+ Year

Education Qualification:

B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Linux Device Driver

Location: Bangalore, Hyderabad, Chennai, Pune

Skills/Experience:

• Exposure to some CPU arch like ARM or x86 or powerpc etc
• NPU Architecture: Broadcom – preferable – Qumran/Jericho family
• 5+ years of active hands-on work with C/C++ with proficient skills
• Exposure to linux device driver programming/ Kernel development /kernel programming is required.
• Good hands-on experience with SW programming language like C and scripting languages like Python, TCL/TL. Network Device driver experience
• Familiarity with Device Driver Development, integration and testing
• Knowledge of OS e.g Linux kernel, drivers and it’s file system etc.
• Good knowledge with SQA process
• Excellent problem-solving and interpersonal skills.
• Good communication skills, verbal and written

Experience (years) : 5-10 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent