Mirafra Technologies recently had the privilege of participating in the DVCon Europe, 2023, in Munich, and what an incredible experience it was!

Senior Manager /Asst. Director – Sales

Location: Bangalore

Job Description:

A senior management role in Sales & Business development with ownership of developing and executing strategic sales plan in line with company’s growth strategy.
Responsible for winning new business (Hunting) & growing existing accounts (Farming), primarily with the GIC (Global In-house Captive) semiconductor customers
Carry the ownership of exploring and closing mid-size to large customer deals including ODCs, KPI and Turnkey projects
Develop and manage pipeline of opportunities across various customers and work with the internal team for their timely fulfilment Work collaboratively across teams – including Engineering and TA to achieve organisational growth plan.
Target and penetrate key prospects and influence decision-makers in winning new logos.
Liaison with internal stakeholders in preparing a response to customer RFI/RFP and participate in bid management.
Participating and representing the company at trade exhibitions, marketing events and conferences.

Job Requirement:

Should have extensive experience & expertise in front-end Sales, Business Development, Client Management & Consulting
Good understanding of the semiconductor technology.
Should have strong relationship at top/senior management level of Fortune-500 technology companies and essentially with all Semiconductor product companies
Experience in building and managing relationships with customer CXO level executives.
Developing and executing sales plan to achieve sales targets and expand the company customer base
Must have done strategic sales for mid-size and large customers including winning large size ODC and Turnkey projects.
Possess extensive knowledge of sales principles and practices, strong negotiations skills and an ability to coach team members.
Proven ability of working in tandem with the internal cross-functional teams
Strong leadership skills.

Experience (years) : 12+ years

Education Qualification:

Engineering graduate in Electronics or Computer science from reputed college/university
MBA in Marketing from a reputed Institution is desirable (not mandatory)

RTL ASIC SoC Architect / Lead RTL Design Engineer

Location: India (Hybrid/Onsite)

Job Description:

• System & Micro-Architecture Definition: Proven ability to translate product requirements and specifications into scalable, power- and performance-optimized micro-architectures.

• SoC Integration & Sub-System Ownership: Extensive experience in top-level SoC integration, clock/reset architecture, power domain planning, and cross-IP coordination.

• Bus Protocols & Interconnects: Strong expertise in industry-standard protocols such as AXI/AHB/APB, coherent interconnects (ACE/CHI preferred), and peripherals including PCIe, USB, Ethernet, CXL, and DDR.

• CPU & Memory Subsystems: Hands-on experience with CPU subsystem integration (ARM/ARC/RISC-V), cache hierarchy, MMU, and memory controller architectures (DDR, LPDDR).

• Low-Power Architecture: Deep understanding of low-power techniques including UPF/CPF, power gating, clock gating, DVFS, multi-voltage designs, and retention strategies.

• RTL Design & Coding Practices: Strong SystemVerilog RTL coding skills with emphasis on reuse, configurability, and synthesis-friendly design.

• Verification & Quality Sign-off: Ability to review and guide verification strategy, static checks test plans, functional coverage, assertions, and regression quality metrics.

• Synthesis, STA & Sign-off: Expertise in synthesis (Design Compiler), static timing analysis, timing closure across multiple PVT corners, and ECO handling.

• Formal & Equivalence Checking: Strong experience with formal verification and logical equivalence checking (LEC).

• DFT & Debug: Good working knowledge of DFT architectures (scan, MBIST, JTAG) and debug/trace infrastructures.

• Post-Silicon Bring-up: Experience with silicon bring-up, lab debugging, silicon validation, and correlation between RTL, simulation, and silicon behavior.

• Chip IO & Packaging: Understanding of chip IO planning, pad ring integration, signal integrity considerations, and packaging constraints.

• Cross-Functional Leadership: Ability to work closely with PD, DV, DFT, firmware, and software teams to ensure seamless execution and delivery.

• Mentoring & Technical Leadership: Proven capability to mentor engineers, review designs, drive best practices, and own delivery of complex SoC programs.

Job Requirement:

• SoC & Micro-Architecture: End-to-end Consumer SoC architecture and micro-architecture design optimized for PPA and real-world use cases.
• CPU & Interconnects: Integration of ARM/ARC/RISC-V CPU subsystems, cache hierarchies, AXI/AHB/APB, and coherent interconnects.
• Memory & High-Speed Interfaces: DDR/LPDDR subsystems and consumer interfaces such as PCIe, USB, Ethernet, CXL, MIPI, and display.
• Low-Power Design: Expertise in UPF-based low-power architecture, clock/power gating, DVFS, and multi-voltage domains.
• RTL, Verification & Sign-off: Strong SystemVerilog RTL, synthesis, STA/timing closure, formal (LEC), and DV/coverage review.
• Post-Silicon & Leadership: Silicon bring-up/debug experience with strong technical leadership and cross-functional collaboration.

Experience (years) : 10+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Mirafra Technologies recently had the privilege of participating in the DVCon Europe, 2023, in Munich, and what an incredible experience it was!

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