Application technology trends

Member Technical Staff

Location: Austin, TX

Roles and Responsibilities:

Perform advanced synthesis setup by analyzing complex library collaterals, diagnosing constraint-related issues, and implementing corrections to optimize the synthesis process for IP and SoC block/toplevel designs. Ensure all Power, Performance, and Area (PPA) metrics and project schedules are met. Collaborate closely with the RTL design team to propose and implement corrections, leveraging deep technical expertise in digital design and hardware description languages. Execute end-to-end Place and Route (PnR) tasks, including floorplanning, power planning, and backend implementation for IP/SoC designs using industry-standard tools such as Cadence Innovus and Synopsys Fusion Compiler. Interface with signoff teams to provide essential design inputs, analyze feedback, and ensure successful signoff closure for IP and SoC products. Develop and deliver highly specialized scripts, comprehensive reports, and customized tool configurations for critical design signoff processes, including: Electro Migration and Current Resistance (EMIR), Physical Design Verification, STA (Static Timing analysis), CLP/Low-Power Closure, Power analysis and optimization, Innovus/Fusion compiler and LEC/FV. Telecommuting and working from home permitted from anywhere in the U.S. Travel and relocation possible to unanticipated client locations throughout the U.S. Domestic travel required approximately 10% of the time to various client sites.

Date posted: 16/06/2026

Skills/Experience:

Bachelor’s or foreign equivalent degree in Electrical Engineering, Electronics Engineering, or Computer Engineering followed by 5 years of experience in the job offered or 5 years of experience in a related occupation of Design Engineer, Consultant or equivalent using tools such as IC Compiler, Innovus, Fusion Compiler, Calibre, Star RC, Primetime, and Genus. Travel and relocation possible to unanticipated client locations throughout the U.S. Domestic travel required approximately 10% of the time to various client sites.

Education Qualification:

Bachelor’s or foreign equivalent degree in Electrical Engineering, Electronics Engineering, or Computer Engineering

STA- Low Power

Location: Bangalore

Job Description:

• Should be able to handle LP-aware synthesis of SoC, tweak the flow to meet PPA targets
• Should be able to debug and resolve RTL2N LEC, N2N, LP-LEC issues
• Should be able to run CLP and resolve gate level CLP violations
• Familiarity with Multi-voltage, multi-power domain based Low power implementation
• Cadence: Genus, LEC, CLP
• Makefile based flow
• Tcl based automation

Experience (years) : 7+ years

Education Qualification:

Bachelors/Master degree in electrical/electronic engineering or similar

STA – Lead

Location: Bangalore

Job Description:

• Should be very strong in Synthesis & Timing concepts
• Should understand .lib very well. Should be aware of all types of libs like NLDM, CCSM, ECSM etc.
• Should have knowledge of DC-topo of similar concepts in other tools (RTL Compiler, talus
• Timing basics should be very strong
• Should understand the clocking structures and concepts very well.
• Should have handled both block and top level. Should know the concepts of budgeting other techniques to handle hierarchical designs
• Should have done both pre and post layout STA
• Should have basic knowledge of Formal verification, Spyglas

Experience (years) : 7+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Design Verification Engineer (FUSA)

Location: Bangalore

Job Description:

• Experience in FuSa Verification
• Experience in Verilog and System Verilog languages
• ISO 26262, Functional Safety,
• Experience in UVM
• Exposure to ISO 26262, fault injection, or diagnostic coverage analysis is desirable for FuSa track

Experience (years) : 4+ years

Education Qualification:

Bachelors/Master degree in electrical/electronic engineering or similar

Senior Manager /Asst. Director – Sales

Location: Bangalore

Job Description:

• A senior management role in Sales & Business development with ownership of developing and executing strategic sales plan in line with company’s growth strategy.
• Responsible for winning new business (Hunting) & growing existing accounts (Farming), primarily with the GIC (Global In-house Captive) semiconductor customers
• Carry the ownership of exploring and closing mid-size to large customer deals including ODCs, KPI and Turnkey projects
• Develop and manage pipeline of opportunities across various customers and work with the internal team for their timely fulfilment Work collaboratively across teams – including Engineering and TA to achieve organisational growth plan.
• Target and penetrate key prospects and influence decision-makers in winning new logos.
• Liaison with internal stakeholders in preparing a response to customer RFI/RFP and participate in bid management.
• Participating and representing the company at trade exhibitions, marketing events and conferences.

Job Requirement:

• Should have extensive experience & expertise in front-end Sales, Business Development, Client Management & Consulting
• Good understanding of the semiconductor technology.
• Should have strong relationship at top/senior management level of Fortune-500 technology companies and essentially with all Semiconductor product companies
• Experience in building and managing relationships with customer CXO level executives.
• Developing and executing sales plan to achieve sales targets and expand the company customer base
• Must have done strategic sales for mid-size and large customers including winning large size ODC and Turnkey projects.
• Possess extensive knowledge of sales principles and practices, strong negotiations skills and an ability to coach team members.
• Proven ability of working in tandem with the internal cross-functional teams
• Strong leadership skills.

Experience (years) : 12+ years

Education Qualification:

• Engineering graduate in Electronics or Computer science from reputed college/university
• MBA in Marketing from a reputed Institution is desirable (not mandatory)

PSV Characterization

Location: Bangalore

Job Description:

• As part of the Post Silicon Engineering group, you will be responsible for developing Test strategy & executing Bench characterization for leading edge High-Speed IO interfaces (PCIe, USB2/3, MIPI- UFS & PLL). You will drive first Silicon debug, qualify semiconductor fabrication process, evaluate parametric performance of SERDES IP’s and perform failure analysis to root-cause a design problem.
• You will be working with system engineering and Hardware applications engineering teams across the globe in a time critical environment.
• Required Experience: 3-6 Years of Post silicon Validation/Electrical Characterization.
• Good understanding of Characterization/SI methodology of High-Speed IO interfaces
• Experience in Instrument handling of JBERT, Oscilloscope, Network-Analyzer, Logic Analyzer, Signal Generators is must.
• Good command in PYTHON
•  C/C++ Programming Knowledge is plus

Experience (years) : 3-6 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

C++ Developer

Location: Hyderabad

Job Description:

• A minimum of 2 years’ experience as a C++ software developer.
• Current knowledge of C++ standards and specifications.
• Proficiency in OOPS, Data Structure & Algoritham
• Extensive experience in deploying software across a variety of platforms and operating systems.
• Superb analytical and problem-solving skills.
• Excellent collaboration and communication skills.
• Great organizational and time management skills.

Experience (years) : 2 - 4 Years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Database management

Location: Hyderabad

Job Description:

•  5+ years hands-on experience with PostgreSQL and relational database management
• Strong proficiency in SQL for complex queries, optimization, and data integrity
• Expertise in database design, performance tuning, and maintenance Technical Skills
• Experience with frontend data visualization tools such as Grafana and Prometheus
• Ability to integrate and configure dashboards for real-time monitoring and analytics
• Familiarity with data pipelines, ETL processes, and API integrations Preferred
• Knowledge of Linux environments and scripting for automation
• Understanding of cloud platforms (AWS, Azure, or GCP) for database hosting
• Strong problem-solving and troubleshooting skills
• VLSI validation exposure

Experience (years) : 5+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

HPC SOFTWARE ENGINEER

Location: Bangalore

Job Description:

• Use proofing tools to identify and understand performance bottlenecks in large code bases, including libraries and HPC and Enterprise applications
•  Port new HPC Applications from multiple scientific domains, do performance benchmarking and deliver optimize recipe.
•  Optimize compiled code, including the use compiler optimizations and the leverage of performant libraries
• Collaborate with software engineers to enable them to understand and improve code performance
• Build software tools for the most advanced HPC (High Performance Compute) and AI platforms in the world

Job Requirement:

• Excellent problem-solving skills, including the ability to flexibly learn new technical skills and resolve novel and unforeseen issues
• Self-managing, being able to work with limited supervision on multiple complex tasks and deliver goals on time
• Good communication and team working skills, able to efficiently meet individual and team goals as part of a distributed team
• Experience of parallel languages and paradigms, such as OpenMP or MPI
• Prior experience of scripting such as Python, Shell & Ansible is desirable.
• Experience in Database and upstreaming applications are add-ons.
• Knowledge of build systems, Spack and source code control systems is desirable

Experience (years) : 4-10 Years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Physical Design Engineer

Location: Bangalore / Noida

Job Description:

• Must hands on experience with a solid complex (SOC/sub-systems/SWRPs) implementation and strong understanding in PG/floorplan and physical design flows and methodologies, place and route using tools such as Innovus & FC
• Strong scripting skills in Innovus- TCL, and Python/Perl(optional)
• Top down floorplan and Power Grid understanding for development methodology is a must
• Experience with signoff convergence(STA, EMIR, PV) of the implemented subsystem
• Block level Timing Signoff and ECO generation
• Block level Power signoff
• Good skill on Automation (Perl/Tcl/Awk/Python
• Good in communication skill as he/she would be single point of contact for client.

Experience (years) : 4+ years

Education Qualification:

BTech/ MTech  Electrical/Electronics/Computer Science Engineering or Equivalent.

Formal Verification

Location: Hyderabad

Job Description:

• Strong experience in Formal Verification methodologies
•  Hands-on expertise in SystemVerilog Assertions (SVA)
•  Solid understanding of RTL design and micro-architecture
•  Experience with equivalence checking (LEC/SEC)
•  Knowledge of CDC/RDC verification
•  Good debugging skills using counterexamples and traces

Job Requirement:

• Jasper Gold experience, CC checks, Property checks and IOMUX verification

Experience (years) : 4-10 yrs

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

FPGA Engineer

Location: Hyderabad

Job Description:

• Strong in digital design.
• Strong in Xilinx Vivado IP & IPI tools till bit-generation.
•  Knowledge of VHDL/Verilog/System Verilog.
•  Knowledge of Validating IP/IP Example designs on Xilinx boards, debugging of failures on target boards, board bring up.
•  Proficiency in Linux environment.
•  Good communication skills.

Experience (years) : 3-6 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Design Verification(Ethernet/Wifi/BT)

Location: Pune

Job Description:

• Develop verification plans for Ethernet, Wi-Fi, and Bluetooth IPs
• Build and maintain SystemVerilog/UVM-based verification environments
• Verify protocol compliance and interoperability
•  Create directed and constrained-random tests
•  Develop SystemVerilog Assertions (SVA) and functional coverage
•  Debug complex protocol issues using waveforms, logs, and traces
•  Perform end-to-end data path verification and stress testing
•  Collaborate with RTL, firmware, architecture, and validation teams
•  Drive coverage closure (functional, code, assertion)

Experience (years) : 4+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Design Verification(High Speed Protocol)

Location: Bangalore

Job Description:

• PCIE/DDR/LPDDR/CXL/UCIE/Ethernet are good to have protocols, Arm experience, GLS
• Initial work at subsystem level followed by SoC level execution
• Expertise on Ethernet protocol/Expertise on packet processing in networking data path.
• High speed ethernet experience 400G+ is preferred.

Experience (years) : 4+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Design Verification (Cache)

Location: Bangalore

Job Description:

• Strong knowledge of cache architecture & memory hierarchy
• Hands-on experience with SystemVerilog & UVM
• Good understanding of SoC interconnects (AXI / ACE / CHI)
• Experience in protocol verification and debug
• Solid fundamentals in computer architecture
• Familiarity with coverage-driven verification methodologies

Experience (years) : 4+ years

Education Qualification:

BE/ME

Design Verification(SOC)

Location: Bangalore

Job Description:

• Verification engineer with a knowledge of SoC integration verification, SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx/AI accelarator integration verification in SoC RTL.
• Your key responsibilities will include writing test plans, defining test methodologies, developing C based software tests, SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues.
• Working with project management and leads on planning tasks, schedules, and reporting progress
• Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development

Job Requirement:

Proven understanding of digital hardware verification language Verilog/System Verilog HDL.

Experience (years) : 5+ years

Education Qualification:

BE/ME

Analog Layout

Location: Bangalore / Hyderabad

Job Description:

• TSMC 16/12nm,7nm,5nm,3nm and below (other foundries are also fine like Intel, Samsung, GF). Preferably TSMC 5nm/3nm experience.
• Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.
• Verification flows – LVS/DRC/DFM/Antenna check/EMIR experience.
• Responsible for on-time delivery of block-level layouts of acceptable quality.
• Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must.
• BE or MTech in Electronics/VLSI Engineering
• Good communications skills as we work with cross-functional teams.
• Share the profiles who have good hands-on experience in recent times on lowers nodes.
• TM should work independently.
• 4 to 8 years of experience – flexible
• If a candidate has HBM experience, it is an added advantage. Analog blocks like Regulators/Charge pumps/Power Management etc..

Job Requirement:

TSMC 2nm or 3 nm

Experience (years) : 4-8 years

Education Qualification:

BTech

Analog Circuit Design

Location: Bangalore / Hyderabad

Job Description:

• High speed DDR IO Circuit Design JD: (Experience level 2 year to 6year)
• Strong fundamental in Circuit design. Knowledge of finfet.
• Work experience in high speed transreceiver, Prior work experience in high speed TX, RX.
• Knowledge of ESD, Latchup.
• Experience in layout related issue. Strong debug capability.
• Experience in .lib/Verilog view generation and validation.
• Scripting knowledge is Plus.

Experience (years) : 5-9 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

IO Layout

Location: Bangalore

Job Description:

• Very Good Knowledge on GPIO layouts and performing Layout verifications.
• Good Exposure to Technologies of GF 55nm , UMC 55nm , TSMC 28nm, TSMC 12nm etc.
• Should have Solid experience in Layout design and Verifications of all the blocks of a GPIO library like Driver, predriver, receiver, ESD clamps.
• Should be in position to technically drive the Layout Implementation starting with floorplanning, placement , IO ring Implementation , IO Bus design .
• Very good hands on knowledge on the Cadence Virtuoso layout verification suite relevant to the above mentioned technologies.
• Very good understanding of ESD & LU concepts and corresponding Layout Implementation strategies and challenges.
• Working (hands on) knowledge of Linux OS and Unix Shell & PERL scripting will be a plus.
• Good team player in a multi-site work environment
• Working knowledge with load sharing systems like LSF will be a plus. Very Good Knowledge on GPIO layouts and performing Layout verifications.
• Good Exposure to Technologies of GF 55nm , UMC 55nm , TSMC 28nm, TSMC 12nm etc.
• Should have Solid experience in Layout design and Verifications of all the blocks of a GPIO library like Driver, predriver, receiver, ESD clamps.
• Should be in position to technically drive the Layout Implementation starting with floorplanning, placement , IO ring Implementation , IO Bus design .
• Very good hands on knowledge on the Cadence Virtuoso layout verification suite relevant to the above mentioned technologies.
• Very good understanding of ESD & LU concepts and corresponding Layout Implementation strategies and challenges.
• Working (hands on) knowledge of Linux OS and Unix Shell & PERL scripting will be a plus.
• Good team player in a multi-site work environment
• Working knowledge with load sharing systems like LSF will be a plus.

Experience (years) : 4-9 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Memory Layout

Location: Bangalore

Job Description:

• 3-8 years of experience in Memory/Custom Layout design.
• Memory Leafcell layout library design from scratch including top level integration.
• Good knowledge on different types of memory architectures.
• Good knowledge in optimized layout design for better performance.
• Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations.

Job Requirement:

• TSMC 2 & 3 NM

Experience (years) : 5-7 years

STA

Location: Bangalore / Noida

Job Description:

• Should be very strong in Synthesis & Timing concepts
• Should understand .lib very well. Should be aware of all types of libs like NLDM, CCSM, ECSM etc.
• Should have knowledge of DC-topo of similar concepts in other tools (RTL Compiler, talus)
• Timing basics should be very strong
• Should understand the clocking structures and concepts very well.
• Should have handled both block and top level. Should know the concepts of budgeting other techniques to handle hierarchical designs
• Should have done both pre and post layout STA
• Should have basic knowledge of Formal verification, Spyglass

Experience (years) : 3+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

DFT Engineer

Location: India (Hybrid/Onsite)

Job Description:

• Hands on experience in Tessent DFT RTL insertion, DRC checks and debug is a must.
• Hands on experience on Scan Insertion, ATPG, GLS debug, MBIST pattern generation and validation.
• Working knowledge of timing enabled GLS and related debug.
• A basic understanding of DFT IPs like OCC, EDT, SSN, MBIST controllers, IJTAG, IEEE 1600 standard, and Boundary scan.
• Should be able to handle tasks independently.
• The candidate needs to have good debug skills and should be able to communicate related issues to the larger team.
• Working knowledge of TCL is an add-on.

Experience (years) : 4+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

AMS Verification

Location: Bangalore / Hyderabad

Job Description:

• Experience on verifying PMICs or Mixed-Signal products.
• Lead verification of analog and mixed-signal blocks, including but not limited to bandgaps, LDOs, Buck multi-phase switching regulators, comparators, and FuSa monitoring circuits.
• Own the verification plan for assigned blocks or features, ensuring thorough coverage and high-quality tests.
• Develop and/or update models of analog blocks using SV-RNM.
• Understand and verify digital functionalities such as CRC, Clock Monitoring, Register maps, and OTPs, Communication Interfaces.
• Understanding of SystemVerilog including assertions and covergroups.
• Advanced debug skills including RTL and Schematic debug from the top level.
• Create and manage VSIF files for regression.
• Ability to perform coverage analysis using IMC or vManager.
• Makefile scripting is a plus.
• Ability to work independently under broad direction.

Experience (years) : 10+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Design Verification Engineer

Location: Hyderabad

Job Description:

• Must have good knowledge on the verification flows
• Excellent hands-on debug skills and problem solving attitude.
• Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC
• Experience of working on Functional Verification, SoC Verification, Emulation
• Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language OVM/UVM Methodology knowledge and experience.
• Must have good communication skills and the ability to work in a team environment.
• Preferably having experience in architecture such as x86 or ARM domain based SOCs
• Having SOC/IP performance verification background is added plus

Job Requirement:

•Processor / PCI / DDR / Memory/C/C++

Experience (years) : 5-15 years

Education Qualification:

BE / ME

ATE Engineer

Location: Bangalore

Job Description:

• Design, develop, and implement ATE solutions to automate testing for new and existing products
• Create test plans, procedures, and test cases based on product specifications and requirements.
• Write test software scripts using languages such as Python, C++, or similar to interface with ATE hardware.
• Troubleshoot and debug issues in test equipment and software to identify root causes and implement corrective actions.
• Perform analysis of test data and report findings to engineering teams for further improvements.
• Collaborate closely with hardware, firmware, and design teams to ensure test coverage and validation of key product features.
• Maintain and upgrade ATE systems to meet evolving testing needs

Job Requirement:

• Experience in Verigy93K- SMT8

Experience (years) : 3-10 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Functional Validation

Location: Hyderabad/ Chennai

Job Description:

•  Experience on JTAG debuggers (e.g., Lauterbach)
•  Familiarity with CPU uArch and coherent fabric
•  Post silicon debug expertise.
•  Familiarity with ARMv8/ARMv9
• Strong Experience on programming in C
• Experience on system debug, embedded operating systems, or bare metal programming
•  ARM CPU architecture knowledge
•  Pre-Silicon(Emulation) , Post Silicon experience

Experience (years) : 4-10 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

RTL ASIC SoC Architect / Lead RTL Design Engineer

Location: India (Hybrid/Onsite)

Job Description:

• System & Micro-Architecture Definition: Proven ability to translate product requirements and specifications into scalable, power- and performance-optimized micro-architectures.

• SoC Integration & Sub-System Ownership: Extensive experience in top-level SoC integration, clock/reset architecture, power domain planning, and cross-IP coordination.

• Bus Protocols & Interconnects: Strong expertise in industry-standard protocols such as AXI/AHB/APB, coherent interconnects (ACE/CHI preferred), and peripherals including PCIe, USB, Ethernet, CXL, and DDR.

• CPU & Memory Subsystems: Hands-on experience with CPU subsystem integration (ARM/ARC/RISC-V), cache hierarchy, MMU, and memory controller architectures (DDR, LPDDR).

• Low-Power Architecture: Deep understanding of low-power techniques including UPF/CPF, power gating, clock gating, DVFS, multi-voltage designs, and retention strategies.

• RTL Design & Coding Practices: Strong SystemVerilog RTL coding skills with emphasis on reuse, configurability, and synthesis-friendly design.

• Verification & Quality Sign-off: Ability to review and guide verification strategy, static checks test plans, functional coverage, assertions, and regression quality metrics.

• Synthesis, STA & Sign-off: Expertise in synthesis (Design Compiler), static timing analysis, timing closure across multiple PVT corners, and ECO handling.

• Formal & Equivalence Checking: Strong experience with formal verification and logical equivalence checking (LEC).

• DFT & Debug: Good working knowledge of DFT architectures (scan, MBIST, JTAG) and debug/trace infrastructures.

• Post-Silicon Bring-up: Experience with silicon bring-up, lab debugging, silicon validation, and correlation between RTL, simulation, and silicon behavior.

• Chip IO & Packaging: Understanding of chip IO planning, pad ring integration, signal integrity considerations, and packaging constraints.

• Cross-Functional Leadership: Ability to work closely with PD, DV, DFT, firmware, and software teams to ensure seamless execution and delivery.

• Mentoring & Technical Leadership: Proven capability to mentor engineers, review designs, drive best practices, and own delivery of complex SoC programs.

 

Job Requirement:

• SoC & Micro-Architecture: End-to-end Consumer SoC architecture and micro-architecture design optimized for PPA and real-world use cases.
• CPU & Interconnects: Integration of ARM/ARC/RISC-V CPU subsystems, cache hierarchies, AXI/AHB/APB, and coherent interconnects.
• Memory & High-Speed Interfaces: DDR/LPDDR subsystems and consumer interfaces such as PCIe, USB, Ethernet, CXL, MIPI, and display.
• Low-Power Design: Expertise in UPF-based low-power architecture, clock/power gating, DVFS, and multi-voltage domains.
• RTL, Verification & Sign-off: Strong SystemVerilog RTL, synthesis, STA/timing closure, formal (LEC), and DV/coverage review.
• Post-Silicon & Leadership: Silicon bring-up/debug experience with strong technical leadership and cross-functional collaboration.

 

Experience (years) : 10+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Design Verification Engineers

Location: Noida

Job Description:

• SOC Verification engineers with 3+ years of experience
• Knowledge of ARM architecture, CPU fundamentals & Cache coherency
• Experience with C/C++, assembly, and scripting languages.
• Familiarity with low-power design and verification
• Develop CDV UVM verification environments at system level
• Verify CPU connectivity to IP blocks
• Develop SoC test plans and test cases and track metrics including code and functional covera

Job Requirement:

• Bachelor’s or Master’s in EE/CS or related field
• 3+ years of SoC in ASIC/FPGA verification experience
• Proficiency in SV and UVM
• Experience with simulation, emulation, and formal verification
• Strong debugging and problem-solving skills

Experience (years) : 3+ Year

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

RTL Design Engineer

Location: India (Hybrid/Onsite)

Job Description:

• Strong in digital IP design using RTL for lower technology nodes [3/4/7nm].
• Experience in micro architect and implementation of complex IP blocks for high-speed designs.
• Optimization of digital logic by analysing timing reports at various stages of ASIC design cycles and defining solutions for path.
• Experience in developing modules for AXI4/5, CHI interfaces.
• Experience in RTL implementation of PCIe/CXL transaction layer or AXI bridging layer.
• Experience in the closure of RTL blocks with quality checks, CDC/RDC/Lint.
• Define and propose innovative solutions to the problem.
• Good team player, proactive in communications, lead proposed solutions to closure.
• Documentation on design approaches, discuss it within the team, come up with conclusive approaches and drive it.
• Co-work with other functional teams on project requirements.

Experience (years) : 4+ years

Education Qualification:

BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field

Multimedia- Video/V4L2

Location: Hyderabad

Job Description:

• Experience in Android and Linux Multimedia frameworks and Linux Kernel development with a focus on V4L2. Experience in Java/perl/python programming.
• Knowledge of software design patterns and multi-threaded programming.
• Knowledge of computer architecture, operating systems, data structures, and basic algorithms, particularly with respect to Linux/Android platforms.
• Software debugging skills in embedded real time operating systems, preferably on Linux platforms
• Additional experience in one or more of the following areas:
• Video usage models including playback, streaming, camcorder, WiFi display, and content protection
• Video compression standards (e.g. H264/H.265/AV1)
• Streaming protocols and implementation (e.g HLS/HTTP/DASH)
• Linux device driver development and debugging (e.g. V4L2)
• Expertise in working with tools and techniques used on Linux (Windbg, JTAG, etc.)
• ARM or other embedded SoC development and debugging

Job Requirement:

• Bachelors\Master’s degree in Engineering, Information Systems, Computer Science, or related field 3-5 years of experience with Programming Language such as C, C++, Java, Python.

Experience (years) : 3+ Year

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Multimedia Audio DSP

Location: Hyderabad

Job Description:

• Experience of 3+years or more on any DSP/Embedded processor with proficiency in C/C++ programming, computer architecture, operating systems and some of the below areas :
• Knowledge of multi-threaded programming.
• Strong software debugging skills in real time operating systems, preferably on DSP platforms.
• Audio use cases (e.g. playback, recording and streaming, etc.).
• Voice use cases (e.g. CS and PS calls).
• Optimization for MIPS, Memory,Audio/speech pre/post processing (e.g. Echo cancellation, Noise suppression, Audio Effects) Audio/speech compression standards (e.g. MP3, AAC, FLAC, AMR, EVS, etc.).
• Android Audio HAL and framework knowledge

Job Requirement:

• Bachelor’s degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Software Engineering or related work experience.
• 3+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc.

Experience (years) : 3+ Year

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Analog Circuit Design

Location: India (Hybrid/Onsite)

Job Description:

• High speed DDR IO Circuit Design JD: (Experience level 2 year to 6year)
• Strong fundamental in Circuit design. Knowledge of finfet.
• Work experience in high speed transreceiver, Prior work experience in high speed TX, RX.
• Knowledge of ESD, Latchup.
• Experience in layout related issue. Strong debug capability.
• Experience in .lib/Verilog view generation and validation.
• Scripting knowledge is Plus.

Skills/Experience:

• Experience with high speed circuits like serializer, deserializer, Rx, Tx,PLL, ADC etc
• Strong VLSI Fundamentals, Circuits design & Digital Systems deep submicron CMOS design based on FinFETs technology.
• Solid fundamentals in circuit analysis and Clock/Memory Circuit design.

Experience (years) : 2+ Year

Education Qualification:

BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

IO Layout

Location: India (Hybrid/Onsite)

Job Description:

• Very Good Knowledge on GPIO layouts and performing Layout verifications.
• Good Exposure to Technologies of GF 55nm , UMC 55nm , TSMC 28nm, TSMC 12nm etc.
•  Should have Solid experience in Layout design and Verifications of all the blocks of a GPIO library like Driver, predriver, receiver, ESD clamps.
•  Should be in position to technically drive the Layout Implementation starting with floorplanning, placement , IO ring Implementation , IO Bus design .
•  Very good hands on knowledge on the Cadence Virtuoso layout verification suite relevant to the above mentioned technologies.
•  Very good understanding of ESD & LU concepts and corresponding Layout Implementation strategies and challenges.
•  Working (hands on) knowledge of Linux OS and Unix Shell & PERL scripting will be a plus.
•  Good team player in a multi-site work environment
•  Working knowledge with load sharing systems like LSF will be a plus. Very Good Knowledge on GPIO layouts and performing Layout verifications.
•  Good Exposure to Technologies of GF 55nm , UMC 55nm , TSMC 28nm, TSMC 12nm etc.

 

Experience (years) : 3+ Year

Education Qualification:

BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

PMIC Characterization

Location: Bangalore, Hyderabad, Noida

Job Description:

• Good knowledge on PMIC (power management IC) hardware validation engineers.
• NPU Architecture: Broadcom – preferable – Qumran/Jericho family
• Labview expertise is a good to have expertise.
• Good understanding of Switching and Linear Voltage Regulators

Experience (years) : 2 - 7 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

FPGA Design Engineer

Location: Bangalore, Hyderabad, Noida

Job Description:

• Good Experience with Xilinx FPGA.
• Should be well aware of RTL logic.
• Well versed with Vivado tool and associated IP’
• Well versed with LUT considerations in FPGA design
• Well versed with FPGA simulation and testing methods
• Well versed with FPGA debug using Xilinx JTAG debugger

Experience (years) : 3 - 12 Years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Emulation Engineer

Location: Bangalore, Hyderabad, Noida

Skills/Experience:

• Create emulation models from RTL / Netlist.
• Expertise in mapping designs to Zebu/Palladium/Haps emulation, improving model performance.
• Knowledge of the Palladium flow and experience in migrating design on Palladium.
• Good knowledge of runtime and debug skills.
• Identifying signals and taking wave dumps on palladium platforms and analyse the failures.
• Exposure to ARM/ARC cores and its architecture
• Exposure to AMBA bus architectures like AXI/AHB/APB
• Exposure to bug tracking tools like Jira and version control tools like Github, Bitbucket, GIT
• Exposure to Flash(NAND) and HDD(Hard disk) like storage technologies.
• Experience with Palladium like emulation platforms(Veloce or Zebu or Haps)
• Understanding of JTAG based debuggers

Experience (years) : 3 - 12 Years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Physical Verification Engineer

Location: India (Hybrid/Onsite)

Job Description:

• Hands on experience in Tessent DFT RTL insertion, DRC checks and debug is a must.
• Hands on experience on Scan Insertion, ATPG, GLS debug, MBIST pattern generation and validation.
• Working knowledge of timing enabled GLS and related debug.
• A basic understanding of DFT IPs like OCC, EDT, SSN, MBIST controllers, IJTAG, IEEE 1600 standard, and Boundary scan.
• Should be able to handle tasks independently.
• The candidate needs to have good debug skills and should be able to communicate related issues to the larger team.
• Working knowledge of TCL is an add-on.

Skills/Experience:

• Hands on debugging skills in different physical verification checks like LVS, DRC, ERC, PERC, Antenna, ESD and DFM using Calibre, ICV and Pegasus PV tools
• Knowledge of basic device physics and PV fixing using various PnR tools like Innovus/ICC2 is required.
• Working experience in cutting edge technologies such as 3/4/5nm and 7nm process nodes is desired

Experience (years) : 4+ Year

Education Qualification:

B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Linux Device Driver

Location: Bangalore, Hyderabad, Chennai, Pune

Job Description:

• Exposure to some CPU arch like ARM or x86 or powerpc etc
• NPU Architecture: Broadcom – preferable – Qumran/Jericho family
• 5+ years of active hands-on work with C/C++ with proficient skills
• Exposure to linux device driver programming/ Kernel development /kernel programming is required.
• Good hands-on experience with SW programming language like C and scripting languages like Python, TCL/TL. Network Device driver experience
• Familiarity with Device Driver Development, integration and testing
• Knowledge of OS e.g Linux kernel, drivers and it’s file system etc.
• Good knowledge with SQA process
• Excellent problem-solving and interpersonal skills.
• Good communication skills, verbal and written

Experience (years) : 5-10 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent