DVCon India 2026

Design Verification – Lead

Location: Hyderabad

Job Description:

• Familiarity with SoCs and boot flow would be useful.
• SV UVM based TB environment setup, usage of UVM VIPs.
• Developing UVM sequences, tests, TB bring up and sanity regressions.
• Familiarity with Software development flow including assembly and C is beneficial.
• Knowledge of system-level architecture including buses like AXI/CHI/ACE5, bridges, memory controllers such as DDR5/LPDDR5/DDR4/LPDDR4
• Knowledge of one or more protocols; PCIe, USB, Ethernet
• Sound knowledge on UPF and power domain crossing
• Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi
• Strong expertise in DFT-DV verification, like Scan clear / Mem clear / JTAG / IJTAG / Memory repair, Scan dump, ATPG etc…

Experience (years) : 10+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

DFT Lead

Location: India (Hybrid/Onsite)

Job Description:

• 10+ years of experience in DFT, with at least 5 years in a leadership or managerial role.
• Strong expertise in DFT methodologies, including scan insertion, ATPG, JTAG, BIST, and fault simulation.
• Experience with industry-standard DFT tools such as Mentor Tessent, Synopsys DFTMAX, Cadence Modus, etc.
• Proven track record of leading and delivering large-scale DFT projects.
• Excellent leadership, communication, and interpersonal skills.
• Strong business acumen and experience in P&L management.
• Ability to work collaboratively with cross-functional teams and stakeholders.
• Demonstrated thought leadership through publications, presentations, or industry contributions.

Experience (years) : 10+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Physical Design Lead (RTL–GDSII)

Location: India (Hybrid/Onsite)

Job Description:

• Own complete RTL-to-GDSII flow: floorplan, place, CTS, route, signoff
• Drive PPA optimization, timing, SI, IR/EM closure
• Lead and mentor a team of PD engineers; manage schedules and deliverables
• Interface with RTL, DFT, STA, Verification, Foundry, and Signoff teams
• Handle ECOs, tapeout readiness, and design reviews
• Improve PD methodologies, flows, and automation
• Strong hands-on PD expertise with Innovus / ICC2 / FusionCompiler / Tempus / PrimeTime /Etc.
• Experience in 28nm to 3nm nodes
• Solid scripting skills (TCL, Python/Perl/Shell)
• Proven ownership of block or full-chip tapeouts

Experience (years) : 10+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Design Verification: PAGLS

Location: Bangalore

Job Description:

• Subsystem/SoC level digital verification using constrained-random coverage methodologies at both RTL and Gate Level with UPF
• SOC,GLS and PAGLS
• Experience with Power aware(UPF) verification at RTL And GLS simulations
• Experience in writing Test Plans independently
• Experience in writing/updating Verification Testbench
• Experience with debugging RTL & Gate level simulations
• Experience with Functional Coverage &Code Coverage
• Experience with Scripting in perl, python, tcl
• Experience in planning Verification architecture, review testbench/ testplans with juniors, identify coverage gaps, propose alternate methods for coverage
• Should have been involved in leading a chip DV effort
• Should have been self-driven and quick learner

Experience (years) : 4-12 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

PV Lead

Location: Bangalore

Job Description:

• Lead full-chip Physical Verification (PV) sign-off activities.
• Own and drive DRC, LVS, ERC, and related physical verification checks.
• Lead PV closure from block level through full-chip sign-off.
• Analyze and debug complex DRC/LVS/ERC violations and drive them to closure.
• Work closely with Physical Design teams to resolve physical verification issues.
• Coordinate with Foundry/PDK teams for rule interpretation and verification issues.
• Review and debug verification results from large, complex SoC designs.
• Drive PV schedules, milestones, issue tracking, and sign-off readiness.
• Develop and improve PV methodologies, flows, and automation.
• Support tapeout/sign-off activities and ensure quality of final verification results.
• Mentor and provide technical guidance to PV engineers.
• Collaborate with Physical Design, Custom Layout, CAD, STA, DFT, and other teams.
• Participate in methodology reviews and improve verification turnaround time.

Experience (years) : 10+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

STA Lead

Location: Bangalore

Job Description:

• Lead and execute Static Timing Analysis (STA) for complex SoC designs.
• Perform timing analysis, timing closure, and sign-off activities.
• Analyze and resolve setup, hold, recovery, removal, and clock-related timing violations.
• Develop and debug SDC constraints and timing constraints.
• Work on MCMM (Multi-Corner Multi-Mode) timing analysis and optimization.
• Perform clock timing analysis, including clock skew, latency, and uncertainty.
• Debug timing issues related to logic, placement, routing, congestion, and CTS.
• Collaborate with Physical Design, Synthesis, DFT, and RTL teams for timing closure.
• Review timing reports and identify critical paths and optimization opportunities.
• Handle ECOs for timing closure and sign-off.
• Work with industry-standard STA tools such as Synopsys PrimeTime and/or Cadence Tempus.
• Participate in methodology development, automation, and flow improvements.
• Mentor junior STA engineers and provide technical leadership.

Experience (years) : 8+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

IR Drop

Location: Bangalore

Job Description:

• Strong experience in IR Drop analysis and power integrity for advanced semiconductor designs.
• Hands-on experience with Static/Dynamic IR Drop analysis, power grid analysis, and EM/IR signoff.
• Good knowledge of power planning, power grid, straps, vias, and PG network optimization.
• Experience with industry-standard tools such as Voltus, RedHawk, or equivalent.
• Ability to analyze IR Drop violations and work with Physical Design teams for fixing issues.
• Good understanding of physical design flow, timing, congestion, and power optimization.

Experience (years) : 3+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

AMS Verification Engineer

Location: Bangalore

Job Description:

• Experience in block/full-chip level IR Drop analysis and signoff is preferred.
• Strong debugging, analytical, and problem-solving skills.
• Experience on verifying PMICs or Mixed-Signal products.
• Verification of analog and mixed-signal blocks, including but not limited to bandgaps, LDOs, Buck multi-phase switching regulators, comparators, and FuSa monitoring circuits.
• Develop and/or update models of analog blocks using SV-RNM.
• Understand and verify digital functionalities such as CRC, Clock Monitoring, Register maps, and OTPs, Communication Interfaces.
• Understanding of System Verilog including assertions and cover groups.
• Create and manage VSIF files for regression.
• Ability to perform coverage analysis using IMC or vManager.
• Make file scripting is a plus.
• Ability to work independently under broad direction.

Experience (years) : 4+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Physical Verification

Location: Noida

Job Description:

• Expertise in physical verification (LVS, ERC/PERC, DFM, OPC, Tape Out process) of SoC/Full-chip-level and/or block-level
• Preferably worked on 5nm/7nm/12nm/14nm/16nm/22nm nodes at the major foundries
• Experience in developing sign-off methodology/flow to and supporting a larger team
• Experience in debugging LVS issues at chip-level with complex analog-mixed signal Ips
• Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.)
• Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components
• Expert in EDA Tools: Mentor (Calibre), Synopsys (ICV)
• Experience with ERC rules, PERC rules, ESD rules has an added advantage
• Strong communication skills, problem solving and analytical skills

Experience (years) : 4+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Analog Layout

Location: Germany

Job Description:

• 5-15 years of industry experience in MixedSignal layout design
• Experience in DCDC converter layout development for automotive applications
• Strong experience in BCD technology
• Experience in analog layout design from schematic including effort estimation area estimation optimizing floorplan routing verifications and signoff
• Strong debug and problem solving skills for physical verification of custom layout LVS DRC other Layout checks
• Good understanding of Analog Layout fundamentals such as Matching Electromigration ESD Latchup shielding coupling crosstalk IRdrop active and passive parasitic devices etc
• Familiar with EDA tools like Cadence Virtuoso Editor Calibre
• Excellent communication good interpersonal skills and critical thinking abilities to resolve the issue technically and professionally
• Holding Bachelors or Masters degree in electrical Electronic Engineering

Experience (years) : 4-10 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Physical Design Engineer

Location: Bangalore / Hyderabad /Noida

Job Description:

• Perform end-to-end Physical Design implementation from Netlist to GDSII.
• Handle Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Verification.
• Achieve timing closure across all MMMC scenarios.
• Perform congestion analysis, optimization, and routing closure.
• Optimize designs for Power, Performance, and Area (PPA).
• Work on Signal Integrity (SI), Crosstalk, IR Drop, and Electromigration (EM) analysis and closure.
• Perform ECO implementation for timing and functional fixes.
• Analyze and resolve DRC, LVS, and Antenna violations.
• Collaborate with RTL, Synthesis, DFT, STA, and Verification teams to resolve implementation issues.
• Support physical design sign-off activities and tape-out.

Experience (years) : 4+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

AI Architect — Chip Design / Semiconductor Background

Location: Bangalore

Job Description:

• Define the AI architecture strategy spanning data pipelines model selection and deployment for semiconductor design use cases
• Architect and prototype AIML solutions that augment backend design STA DFT and physical verification flows eg PPA optimization automated DFT insertion logreport analysis predictive timing closure
• Integrate LLMs and ML models into existing EDA toolchains Innovus Tempus PrimeTime Calibre etc and LinuxTCLPython scripting environments
• Architect agentic AI workflows agents that plan execute and iterate across multistep design tasks debug triage ECO loop automation constraint generation regression analysis with appropriate humanintheloop checkpoints
• Design multiagent systems that orchestrate specialized agents across the RTLtoGDSII flow integrating tool calls to EDA engines scripts and internal knowledge bases
• Build robust agent infrastructure toolfunctioncalling interfaces context and memory management state handling and guardrails for reliability in engineeringcritical applications
• Evaluate and benchmark foundation models finetuning approaches RAG pipelines and agent orchestration patterns
• Establish an agent control plane policy approval gates observability and audit trails before autonomous agents touch production systems
• Partner with delivery teams and clients to translate AI capabilities into productized service offerings
• Establish MLOps practices model governance and scalable infrastructure onpremcloudhybrid
• Mentor engineers on AIML adoption and build the technical foundation for an AI Center of Excellence

Experience (years) : 10+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Program Manager

Location: Bangalore

Job Description:

• 5 years of Program Management or related work experience.
• Bachelors degree in Engineering Computer Science or related field
• 4 years of Program Management or related work experience
• The successful candidate will own technical program management for our PD Engineering teams development and delivery to a key clients  SoC Responsibilities will include Coordinate plan and drive Physical Design IP development testing and delivery to SoC alongside the smartest minds in the industry
• Negotiate schedule scope and line up resources to meet aggressive schedules to deliver best in class efficient highperformance SOCs
• Organize and lead interdepartmental discussions to set project milestonesschedules plans of records define project tasks establish program policies and processes
• Responsible for managing IPSoC relationship
• Troubleshoot program issues and help to develop alternative program tasks schedules milestones resource plans processes etc to resolve program issues and conflicts
• Determine risks develop mitigation strategies and communicate information to internal and external key stakeholders Must be able to proactively drive and solve problems to solutions
• Rollup and report regularly to senior managementexecutives on key development milestones budget metrics risks and mitigation plans
• Develop processes to increase the productivity and efficiency of the team
• Manage teams through design development validation test manufacturing deployment and sustaining activities for hardware products
• Be an advocate for the program in crossfunctional and stakeholder meetings

Experience (years) : 7+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

DFT Lead

Location: Bangalore

Job Description:

• Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.
• Lead implementation and verification of DFT features like:
• Scan insertion and compression (e.g., EDT)
• ATPG pattern generation and fault grading
• MBIST and Logic BIST insertion and validation
• Boundary scan (IEEE 1149.1/1149.6), IJTAG (1687)
• Manage end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up.
• Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.
• Perform pattern generation, fault simulation, and debug test coverage gaps.
• Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.
• Support silicon bring-up, test vector validation on ATE, and yield optimization.
• Mentor and guide junior DFT engineers; conduct design reviews and training sessions.
• Develop and maintain DFT automation scripts and infrastructure.

Experience (years) : 7+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Analog Circuit Design

Location: Bangalore

Job Description:

• Expert in EDA Tools: Mentor (Calibre), Synopsys (ICV)
• Experience with ERC rules, PERC rules, ESD rules has an added advantage
• Strong communication skills, problem solving and analytical skills
• Experience in analog/mixed-signal IC design, particularly switching regulator circuits and DC-DC converters.
• Hands-on experience with buck converter and/or switching DC-DC converter design, including high-voltage designs
• Good understanding of Peak Current Mode Control (PCMC) and associated control-loop concepts.
• Experience with converter-level architecture, system integration, and top-level analog simulations.
• Ability to debug circuit performance issues across sub-block and top-level designs.
• Experience working with and reviewing the work of junior engineers and external design resources.
• Proficiency with industry-standard analog design and simulation tools such as Cadence Virtuoso, Spectre, and associated extraction/verification tools.
• Experience with post-layout and post-Silicon debug and design bring-up would be added advantage

Experience (years) : 4-6 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Synthesis

Location: Bangalore / Hyderabad

Job Description:

• Good understanding of ASIC design flow.
• Hands on experience in synthesis and static timing analysis.
• Proficiency with Synopsys DC & PT tools and Verilog/VHDL is a must.
• Experience in Perl, TCL and shell scripting is desirable.
• Excellent interpersonal & analytical skills with ability to work independently.
• Placement/Power aware synthesis using Synopsys & Cadence tools (DCG/NXT/FC, Genus).
• Constraints development, Formal Verification, CECO, Static Timing Analysis & timing closure.
• Work closely with design team to come up with preplacement requirements & timing constraints.
• Work closely with physical design team for floorplan, placement & timing reviews.
• Work closely with cross-functional teams to review standard cell profile, timing models & memory models.
• Expertise in physical verification (LVS, ERC/PERC, DFM, OPC, Tape Out process) of SoC/Full-chip-level and/or block-level.
• Preferably worked on 5nm/7nm/12nm/14nm/16nm/22nm nodes at the major foundries.
• Experience in developing sign-off methodology/flow to and supporting a larger team

Experience (years) : 3+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Display Validation

Location: Bangalore

Job Description:

• Experience on JTAG debuggers (e.g., Lauterbach)
• Familiarity with CPU uArch and coherent fabric
• Post silicon debug expertise.
•  Familiarity with ARMv8/ARMv9 Strong Experience on programming in C
• Experience on system debug, embedded operating systems, or bare metal programming, tensor processor unit-TPU ARM CPU architecture knowledge Pre-Silicon(Emulation) , Post Silicon experience

Experience (years) : 4-10 Years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

TPU Validation

Location: Bangalore

Job Description:

• Experience on JTAG debuggers (e.g., Lauterbach)
• Familiarity with CPU uArch and coherent fabric
• Post silicon debug expertise.
•  Familiarity with ARMv8/ARMv9 Strong Experience on programming in C
• Experience on system debug, embedded operating systems, or bare metal programming, tensor processor unit-TPU ARM CPU architecture knowledge Pre-Silicon(Emulation) , Post Silicon experience

Experience (years) : 3-10 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Memory Layout Design Engineer

Location: Bangalore

Job Description:

• Development of key building blocks of memory architecture such as Row Decoder, IO, Control.
• Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing.
• Knowledge of EM/IR requirements. Compiler level integration, verification of Compiler/Custom memories.
• Should possess good knowledge on CMOS fabrication process, foundries and challenges in latest technology nodes

Experience (years) : 2-8 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

IC Package Engineer

Location: Bangalore

Job Description:

• Design Package layouts for multiple applications.
• Able to handle constraints-driven IC Package layout methodology.
• Having basic understanding on Signal integrity and power integrity concepts.
• Conduct layout reviews with internal layout and design teams.
• Release IC Package layout drawings to the various design teams and coordinates their layout activities by ensuring compliance with the Design rules.
• Design Rules Check (DRC): Perform design rule checks to ensure that the layout meets the specific manufacturing and design guidelines.
• Perform quality assurance by using CAM350 Gerber validation toolsDeliver Accurate layout designs by having basic Knowledge on Design for Manufacturing (DFM): Consider manufacturability and DFA : Craft for Assembly and DFT: Design for Testing.
• Proven oral and written communication skills to connect with Customers and Multi-functional teams.

Experience (years) : 8+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

PSV Characterization

Location: Bangalore

Job Description:

• As part of the Post Silicon Engineering group, you will be responsible for developing Test strategy & executing Bench characterization for leading edge High-Speed IO interfaces (PCIe, USB2/3, MIPI- UFS & PLL). You will drive first Silicon debug, qualify semiconductor fabrication process, evaluate parametric performance of SERDES IP’s and perform failure analysis to root-cause a design problem.
• You will be working with system engineering and Hardware applications engineering teams across the globe in a time critical environment.
• Required Experience: 3-6 Years of Post silicon Validation/Electrical Characterization.
• Good understanding of Characterization/SI methodology of High-Speed IO interfaces
• Experience in Instrument handling of JBERT, Oscilloscope, Network-Analyzer, Logic Analyzer, Signal Generators is must.
• Good command in PYTHON
•  C/C++ Programming Knowledge is plus

Experience (years) : 3-6 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

C++ Developer

Location: Hyderabad

Job Description:

• A minimum of 2 years’ experience as a C++ software developer.
• Current knowledge of C++ standards and specifications.
• Proficiency in OOPS, Data Structure & Algoritham
• Extensive experience in deploying software across a variety of platforms and operating systems.
• Superb analytical and problem-solving skills.
• Excellent collaboration and communication skills.
• Great organizational and time management skills.

Experience (years) : 2 - 4 Years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Database management

Location: Hyderabad

Job Description:

•  5+ years hands-on experience with PostgreSQL and relational database management
• Strong proficiency in SQL for complex queries, optimization, and data integrity
• Expertise in database design, performance tuning, and maintenance Technical Skills
• Experience with frontend data visualization tools such as Grafana and Prometheus
• Ability to integrate and configure dashboards for real-time monitoring and analytics
• Familiarity with data pipelines, ETL processes, and API integrations Preferred
• Knowledge of Linux environments and scripting for automation
• Understanding of cloud platforms (AWS, Azure, or GCP) for database hosting
• Strong problem-solving and troubleshooting skills
• VLSI validation exposure

Experience (years) : 5+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

HPC SOFTWARE ENGINEER

Location: Bangalore

Job Description:

• Use proofing tools to identify and understand performance bottlenecks in large code bases, including libraries and HPC and Enterprise applications
•  Port new HPC Applications from multiple scientific domains, do performance benchmarking and deliver optimize recipe.
•  Optimize compiled code, including the use compiler optimizations and the leverage of performant libraries
• Collaborate with software engineers to enable them to understand and improve code performance
• Build software tools for the most advanced HPC (High Performance Compute) and AI platforms in the world

Job Requirement:

• Excellent problem-solving skills, including the ability to flexibly learn new technical skills and resolve novel and unforeseen issues
• Self-managing, being able to work with limited supervision on multiple complex tasks and deliver goals on time
• Good communication and team working skills, able to efficiently meet individual and team goals as part of a distributed team
• Experience of parallel languages and paradigms, such as OpenMP or MPI
• Prior experience of scripting such as Python, Shell & Ansible is desirable.
• Experience in Database and upstreaming applications are add-ons.
• Knowledge of build systems, Spack and source code control systems is desirable

Experience (years) : 4-10 Years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Formal Verification

Location: Hyderabad

Job Description:

• Strong experience in Formal Verification methodologies
•  Hands-on expertise in SystemVerilog Assertions (SVA)
•  Solid understanding of RTL design and micro-architecture
•  Experience with equivalence checking (LEC/SEC)
•  Knowledge of CDC/RDC verification
•  Good debugging skills using counterexamples and traces

Job Requirement:

• Jasper Gold experience, CC checks, Property checks and IOMUX verification

Experience (years) : 4-10 yrs

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

FPGA Engineer

Location: Hyderabad

Job Description:

• Strong in digital design.
• Strong in Xilinx Vivado IP & IPI tools till bit-generation.
•  Knowledge of VHDL/Verilog/System Verilog.
•  Knowledge of Validating IP/IP Example designs on Xilinx boards, debugging of failures on target boards, board bring up.
•  Proficiency in Linux environment.
•  Good communication skills.

Experience (years) : 3-6 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Design Verification(High Speed Protocol)

Location: Bangalore

Job Description:

• PCIE/DDR/LPDDR/CXL/UCIE/Ethernet are good to have protocols, Arm experience, GLS
• Initial work at subsystem level followed by SoC level execution
• Expertise on Ethernet protocol/Expertise on packet processing in networking data path.
• High speed ethernet experience 400G+ is preferred.

Experience (years) : 4+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Design Verification (Cache)

Location: Bangalore

Job Description:

• Strong knowledge of cache architecture & memory hierarchy
• Hands-on experience with SystemVerilog & UVM
• Good understanding of SoC interconnects (AXI / ACE / CHI)
• Experience in protocol verification and debug
• Solid fundamentals in computer architecture
• Familiarity with coverage-driven verification methodologies

Experience (years) : 4+ years

Education Qualification:

BE/ME

Design Verification(SOC)

Location: Bangalore

Job Description:

• Verification engineer with a knowledge of SoC integration verification, SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx/AI accelarator integration verification in SoC RTL.
• Your key responsibilities will include writing test plans, defining test methodologies, developing C based software tests, SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues.
• Working with project management and leads on planning tasks, schedules, and reporting progress
• Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development

Job Requirement:

Proven understanding of digital hardware verification language Verilog/System Verilog HDL.

Experience (years) : 5+ years

Education Qualification:

BE/ME

Analog Layout

Location: Bangalore / Hyderabad

Job Description:

• TSMC 16/12nm,7nm,5nm,3nm and below (other foundries are also fine like Intel, Samsung, GF). Preferably TSMC 5nm/3nm experience.
• Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.
• Verification flows – LVS/DRC/DFM/Antenna check/EMIR experience.
• Responsible for on-time delivery of block-level layouts of acceptable quality.
• Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must.
• BE or MTech in Electronics/VLSI Engineering
• Good communications skills as we work with cross-functional teams.
• Share the profiles who have good hands-on experience in recent times on lowers nodes.
• TM should work independently.
• 4 to 8 years of experience – flexible
• If a candidate has HBM experience, it is an added advantage. Analog blocks like Regulators/Charge pumps/Power Management etc..

Job Requirement:

TSMC 2nm or 3 nm

Experience (years) : 4-8 years

Education Qualification:

BTech

STA Engineer

Location: Bangalore / Hyderabad /Noida

Job Description:

• Should be very strong in Synthesis & Timing concepts
• Should understand .lib very well. Should be aware of all types of libs like NLDM, CCSM, ECSM etc.
• Should have knowledge of DC-topo of similar concepts in other tools (RTL Compiler, talus)
• Timing basics should be very strong
• Should understand the clocking structures and concepts very well.
• Should have handled both block and top level. Should know the concepts of budgeting other techniques to handle hierarchical designs
• Should have done both pre and post layout STA
• Should have basic knowledge of Formal verification, Spyglass

Experience (years) : 3+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

DFT Engineer

Location: Bangalore

Job Description:

• Hands on experience in Tessent DFT RTL insertion, DRC checks and debug is a must.
• Hands on experience on Scan Insertion, ATPG, GLS debug, MBIST pattern generation and validation.
• Working knowledge of timing enabled GLS and related debug.
• A basic understanding of DFT IPs like OCC, EDT, SSN, MBIST controllers, IJTAG, IEEE 1600 standard, and Boundary scan.
• Should be able to handle tasks independently.
• The candidate needs to have good debug skills and should be able to communicate related issues to the larger team.
• Working knowledge of TCL is an add-on.

Experience (years) : 4+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Design Verification Engineer

Location: Hyderabad

Job Description:

• Must have good knowledge on the verification flows
• Excellent hands-on debug skills and problem solving attitude.
• Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC
• Experience of working on Functional Verification, SoC Verification, Emulation
• Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language OVM/UVM Methodology knowledge and experience.
• Must have good communication skills and the ability to work in a team environment.
• Preferably having experience in architecture such as x86 or ARM domain based SOCs
• Having SOC/IP performance verification background is added plus

Job Requirement:

•Processor / PCI / DDR / Memory/C/C++

Experience (years) : 5-15 years

Education Qualification:

BE / ME

ATE Engineer

Location: Bangalore

Job Description:

• Design, develop, and implement ATE solutions to automate testing for new and existing products
• Create test plans, procedures, and test cases based on product specifications and requirements.
• Write test software scripts using languages such as Python, C++, or similar to interface with ATE hardware.
• Troubleshoot and debug issues in test equipment and software to identify root causes and implement corrective actions.
• Perform analysis of test data and report findings to engineering teams for further improvements.
• Collaborate closely with hardware, firmware, and design teams to ensure test coverage and validation of key product features.
• Maintain and upgrade ATE systems to meet evolving testing needs

Job Requirement:

• Experience in Verigy93K- SMT8

Experience (years) : 3-10 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

RTL ASIC SoC Architect / Lead RTL Design Engineer

Location: India (Hybrid/Onsite)

Job Description:

• System & Micro-Architecture Definition: Proven ability to translate product requirements and specifications into scalable, power- and performance-optimized micro-architectures.
• SoC Integration & Sub-System Ownership: Extensive experience in top-level SoC integration, clock/reset architecture, power domain planning, and cross-IP coordination.
• Bus Protocols & Interconnects: Strong expertise in industry-standard protocols such as AXI/AHB/APB, coherent interconnects (ACE/CHI preferred), and peripherals including PCIe, USB, Ethernet, CXL, and DDR.
• CPU & Memory Subsystems: Hands-on experience with CPU subsystem integration (ARM/ARC/RISC-V), cache hierarchy, MMU, and memory controller architectures (DDR, LPDDR).
• Low-Power Architecture: Deep understanding of low-power techniques including UPF/CPF, power gating, clock gating, DVFS, multi-voltage designs, and retention strategies.
• RTL Design & Coding Practices: Strong System Verilog RTL coding skills with emphasis on reuse, configurability, and synthesis-friendly design.
• Verification & Quality Sign-off: Ability to review and guide verification strategy, static checks test plans, functional coverage, assertions, and regression quality metrics.
• Synthesis, STA & Sign-off: Expertise in synthesis (Design Compiler), static timing analysis, timing closure across multiple PVT corners, and ECO handling.
• Formal & Equivalence Checking: Strong experience with formal verification and logical equivalence checking (LEC).
• DFT & Debug: Good working knowledge of DFT architectures (scan, MBIST, JTAG) and debug/trace infrastructures.
• Post-Silicon Bring-up: Experience with silicon bring-up, lab debugging, silicon validation, and correlation between RTL, simulation, and silicon behaviour.
• Chip IO & Packaging: Understanding of chip IO planning, pad ring integration, signal integrity considerations, and packaging constraints.
• Cross-Functional Leadership: Ability to work closely with PD, DV, DFT, firmware, and software teams to ensure seamless execution and delivery.
• Mentoring & Technical Leadership: Proven capability to mentor engineers, review designs, drive best practices, and own delivery of complex SoC programs.
• Embedded hardware and software co-design: Collaborate with embedded software and firmware teams to ensure hardware and software co-design, enabling efficient SoC architecture.

Experience (years) : 15+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

RTL Design Engineer

Location: India (Hybrid/Onsite)

Job Description:

• Strong in digital IP design using RTL for lower technology nodes [3/4/7nm].
• Experience in micro architect and implementation of complex IP blocks for high-speed designs.
• Optimization of digital logic by analysing timing reports at various stages of ASIC design cycles and defining solutions for path.
• Experience in developing modules for AXI4/5, CHI interfaces.
• Experience in RTL implementation of PCIe/CXL transaction layer or AXI bridging layer.
• Experience in the closure of RTL blocks with quality checks, CDC/RDC/Lint.
• Define and propose innovative solutions to the problem.
• Good team player, proactive in communications, lead proposed solutions to closure.
• Documentation on design approaches, discuss it within the team, come up with conclusive approaches and drive it.
• Co-work with other functional teams on project requirements.

Experience (years) : 4+ years

Education Qualification:

BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field

Multimedia- Video/V4L2

Location: Hyderabad

Job Description:

• Experience in Android and Linux Multimedia frameworks and Linux Kernel development with a focus on V4L2. Experience in Java/perl/python programming.
• Knowledge of software design patterns and multi-threaded programming.
• Knowledge of computer architecture, operating systems, data structures, and basic algorithms, particularly with respect to Linux/Android platforms.
• Software debugging skills in embedded real time operating systems, preferably on Linux platforms
• Additional experience in one or more of the following areas:
• Video usage models including playback, streaming, camcorder, WiFi display, and content protection
• Video compression standards (e.g. H264/H.265/AV1)
• Streaming protocols and implementation (e.g HLS/HTTP/DASH)
• Linux device driver development and debugging (e.g. V4L2)
• Expertise in working with tools and techniques used on Linux (Windbg, JTAG, etc.)
• ARM or other embedded SoC development and debugging

Job Requirement:

• Bachelors\Master’s degree in Engineering, Information Systems, Computer Science, or related field 3-5 years of experience with Programming Language such as C, C++, Java, Python.

Experience (years) : 3+ Year

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Multimedia Audio DSP

Location: Hyderabad

Job Description:

• Experience of 3+years or more on any DSP/Embedded processor with proficiency in C/C++ programming, computer architecture, operating systems and some of the below areas :
• Knowledge of multi-threaded programming.
• Strong software debugging skills in real time operating systems, preferably on DSP platforms.
• Audio use cases (e.g. playback, recording and streaming, etc.).
• Voice use cases (e.g. CS and PS calls).
• Optimization for MIPS, Memory,Audio/speech pre/post processing (e.g. Echo cancellation, Noise suppression, Audio Effects) Audio/speech compression standards (e.g. MP3, AAC, FLAC, AMR, EVS, etc.).
• Android Audio HAL and framework knowledge

Job Requirement:

• Bachelor’s degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Software Engineering or related work experience.
• 3+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc.

Experience (years) : 3+ Year

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

IO Layout

Location: India (Hybrid/Onsite)

Job Description:

• Very Good Knowledge on GPIO layouts and performing Layout verifications.
• Good Exposure to Technologies of GF 55nm , UMC 55nm , TSMC 28nm, TSMC 12nm etc.
•  Should have Solid experience in Layout design and Verifications of all the blocks of a GPIO library like Driver, predriver, receiver, ESD clamps.
•  Should be in position to technically drive the Layout Implementation starting with floorplanning, placement , IO ring Implementation , IO Bus design .
•  Very good hands on knowledge on the Cadence Virtuoso layout verification suite relevant to the above mentioned technologies.
•  Very good understanding of ESD & LU concepts and corresponding Layout Implementation strategies and challenges.
•  Working (hands on) knowledge of Linux OS and Unix Shell & PERL scripting will be a plus.
•  Good team player in a multi-site work environment
•  Working knowledge with load sharing systems like LSF will be a plus.

 

Experience (years) : 3+ Year

Education Qualification:

BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

PMIC Characterization

Location: Bangalore, Hyderabad, Noida

Job Description:

• Good knowledge on PMIC (power management IC) hardware validation engineers.
• NPU Architecture: Broadcom – preferable – Qumran/Jericho family
• Labview expertise is a good to have expertise.
• Good understanding of Switching and Linear Voltage Regulators

Experience (years) : 2 - 7 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Emulation Engineer

Location: Bangalore, Hyderabad, Noida

Job Description:

• Create emulation models from RTL / Netlist.
• Expertise in mapping designs to Zebu/Palladium/Haps emulation, improving model performance.
• Knowledge of the Palladium flow and experience in migrating design on Palladium.
• Good knowledge of runtime and debug skills.
• Identifying signals and taking wave dumps on palladium platforms and analyse the failures.
• Exposure to ARM/ARC cores and its architecture
• Exposure to AMBA bus architectures like AXI/AHB/APB
• Exposure to bug tracking tools like Jira and version control tools like Github, Bitbucket, GIT
• Exposure to Flash(NAND) and HDD(Hard disk) like storage technologies.
• Experience with Palladium like emulation platforms(Veloce or Zebu or Haps)
• Understanding of JTAG based debuggers

Experience (years) : 3 - 12 Years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Linux Device Driver

Location: Bangalore, Hyderabad, Chennai, Pune

Job Description:

• Exposure to some CPU arch like ARM or x86 or powerpc etc
• NPU Architecture: Broadcom – preferable – Qumran/Jericho family
• 5+ years of active hands-on work with C/C++ with proficient skills
• Exposure to linux device driver programming/ Kernel development /kernel programming is required.
• Good hands-on experience with SW programming language like C and scripting languages like Python, TCL/TL. Network Device driver experience
• Familiarity with Device Driver Development, integration and testing
• Knowledge of OS e.g Linux kernel, drivers and it’s file system etc.
• Good knowledge with SQA process
• Excellent problem-solving and interpersonal skills.
• Good communication skills, verbal and written

Experience (years) : 5-10 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent