1. Full Chip Verification of a Storage Area Network (SAN) SOC

The customer:
Customer is a world leader of enterprise-class products that intelligently connect storage, servers and networks.

The product:
It is a multi-million gate storage processor chip which supports multiple protocols and had applications in intelligent storage I/O, server clustering, high performance data networking and intelligent storage platform solutions, including storage virtualization. It is a complex chip with 15 different blocks, 7 processors at 350 MHz, with multiple clock domains.

Mirafra's responsibility:

• Functional verification of 5 blocks.
• Part of system level verification.

The challenges:

• Defining verification methodology for each block.
• Ever changing specs and Interfaces across various blocks.
• Short ramp-up time to understand the complex DUT.
• Micro architecture was evolving.
• Communicating across the globe as Architect and Designers were sitting in USA .

 

The solution:

Verification Environment Development

• Proposed and developed advanced methodology ( Vera ) based Verification environment for each block.
• Development of testbench using Vera HVL.
• The testbench development was carried out in Vera using knobs to support the random stimulus generation. Test-cases and testbench made compatible for Gate-level simulation
• Constrained random scenarios were identified.
• Few directed scenarios were identified
• All test benches were fully regressionable.
• We helped documenting the design specification and reported documentation bugs.

Testcases development and analysis

• Test-cases were developed as per test plan.
• Test-cases analysis using Virsim, Debussy
• Failure test case analysis is carried out with Debussy and Virsim and figure out the problem is in the testbench or design, if the problem is in the testbench fix it and if it is in design report the in Bugtracks

Bug Report

• Bugs were reported with clear documentation of bug , seed & CVS Tag to reproduce the bug, with path where to look for logs/dump and define the priority of bugs
• As we started filing the bug, the design implementation and specification started changing; hence, we were in a constant process of reviewing the test-plan and modification in verification environment and test-cases.

 

Summary & Achievements:

The Mirafra team of 7 Engineers finished this 40 million gates verification in 18 months following was the comments from VP of Engineering…

“Mirafra has an exceptional team that owned and delivered our complex verification needs. We are very pleased with the quality of their work and the dedication shown by their team. We will not hesitate to use their services for our future verification needs”

-- VP Engineering

2. Block Level Verification of Buffer Queue Manager Block of SAN SOC

The customer:
Customer is a world leader of enterprise-class products that intelligently connect storage, servers and networks.

Description of Block:
The block parses the incoming packet, extracts some fields from it, and concatenates them to form a key. It uses this key to extract a flow id from a hash table implemented in an external memory. The block also implements packet classification to decide on outgoing ports and complex arbitration schemes based on incoming port and packet types.

The challenges:

• The block is highly programmable. For example the positions of all the fields extracted can be programmed.
• The functionality was quite complex. For example, it implements the hash table traversal in hardware.
• New features were getting added till the last moment.
• The ‘ C ' model, which was maintained by the software team, fell out of synch with the changes in RTL.

 

The solution:

The verification environment was designed in VCS-NTB. The environment implemented a complete functional model of the device in the scoreboard. This made it possible to randomize all the configurations independently. The protocols were checked using interface assertions. The monitors were written to be usable at system level as well.

Code coverage was run on the RTL and all the reachable code was covered. High level of condition coverage was also achieved.

Summary & Achievements:

The block was successfully integrated into the SOC. FPGA prototype and the final chip did not reveal any bugs in the block in the chip.