Mirafra has been successful in building a highly motivated and talented team of engineers. Our employees have degrees from the best colleges in India and have experience working in reputed multinational companies. We believe that employees are our most important strength and we are committed to empowering them by giving them voice in company policies and direction. We strive for continued growth through the best training available. We have also set up processes so that employee growth is not taken for granted and reviewed periodically at all levels of management.

Current Openings

Implementation Group

• Physical Design (ICC)

  Physical design of Hard Macros/Partitions of sizes upto 1000K placeable instances from RTL to GDS ,technologies varying from 45nm to 28nm.

  PD activities involve
  Synthesis of RTL to gate netlist, Netlist level optimization , RTL to Gate LEC , Scan chain hookup ,STA Constraints management , Floorplan, IR Drop, Placement/CTS/Routing/Timing Optimization/Timing Closure/DRC/LVS
  
  Tools : Design Compiler , ICC for PnR , Encounter for FloorPlan , Redhawk for IR-Drop, PT/PTSI , Calibre , LEC , Spyglass
Email us your resumes at resumes@mirafra.com


• Physical Design (Magma Talus)

  Physical design of Hard Macros/Partitions of sizes upto 1000K placeable instances from RTL to GDS ,technologies varying from 45nm to 28nm.

  PD activities involve
  Synthesis of RTL to gate netlist, Netlist level optimization , RTL to Gate LEC , Scan chain hookup ,STA Constraints management , Floorplan, IR Drop, Placement/CTS/Routing/Timing Optimization/Timing Closure/DRC/LVS
  
  Tools : Design Compiler , Talus for PnR , Encounter for FloorPlan , Redhawk for IR-Drop, PT/PTSI , Calibre , LEC , Spyglass
Email us your resumes at resumes@mirafra.com


• STA/Synthesis

  Strong Skill in STA/Synthesis with Design Compiler/Prime Time Experience

Email us your resumes at resumes@mirafra.com


• DFT Requirement

  Required Skills: Scan insertion, ATPG, Pattern Simulation with and without timing annotation.

  Experience on Scan compression techniques, Memory BIST, Boundary Scan, JTAG concepts, basic understanding of Tester requirements, basics of synthesis and timing. Knowledge of formal verification. Exposure to SoC level DFT.
  Proficiency with MentorGraphics/Synopsys EDA tools like Fast scan, TestKompress, TetraMax, DFTMax, DFTCompiler, DFTAdvisor. Expertise with memory BIST insertion tools preferably LogicVision MBIST/Mentor’s MBISTArchitect.
  
Email us your resumes at resumes@mirafra.com


• RTL Design & Integration

  The candidate should be proficient in the following skills:

  1. RTL Coding in Verilog/VHDL 2. Synthesis ( DC ) 3. Spyglass ( lint, DFT, PM, CLK/RST ) 4. SoC integration flows ( integrating multiple IPs and associated QC ) 5. Understanding of Power Management ( voltage domain, power domains, clock domains ) 6. OCP and AXI protocol 7. Misc : Debussy, simulators (mti/ncsim ), perl
  
Email us your resumes at resumes@mirafra.com

Design & Verification Group:

• ARM Based SOC Verification:
  • SOC verification exposure (ARM based preferably) using C
  • Good command over C language Protocols – AXI/AHB/APB Hands on experience on the following.System Verilog based oreboard/coverage/regression development & debug
  • OVM methodology using System Verilog.
  • Exposure to Verilog testbenches and Testcase/regression/coverage development & debug.
  • Preferably – ARM Cortex Exposure.
  • Key Words: ARM,Cortex-A9 exposure, command on C language, Protocols – AXI/AHB/APB
  Email us your resumes at resumes@mirafra.com
  
  
• FE Verification (OVM):
  • Experience in RTL verification and fundamental knowledge in basic verification concepts and issues
  • Hands on experience in RTL verification using OVM
  • Development of OVCs using System Verilog
  • Working experience in OVM verification environment building and integration
  • Developing C/C+ testcases
  • Working knowledge on ARM based design verification, knowhow of AHB/APB bus protocols.
  Email us your resumes at resumes@mirafra.com
  
  

  Self driven, smart, enthusiastic people with engineering degrees from reputed colleges in India and abroad may send their resumes to resumes@mirafra.com